Connect Mesa 6i25 HDR26 with 7I52S HDR50
- juergen-home
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14 Aug 2025 12:53 - 14 Aug 2025 12:56 #333411
by juergen-home
Connect Mesa 6i25 HDR26 with 7I52S HDR50 was created by juergen-home
So I made something up to connect 6i25 HDR26 with 7I52S HDR50.
Some questions about that:
1. Do I have to connect /TX3BENA and /TX0BENA with i/0 pins and config them to low in the .hal file?
2. Can I pull /TX3BENA and /TX0BENA low to GND to save I/O ports?
3. What reason only Differential outputs TX0B and TX3B can be Tristated, do they have a special purpose?
4. Is ENCMUX managed by the 6i25 or do I have to handle the mux things in the .hal myself?
There are a few more questions but this is enough for today.
(my configuration so far was in www.forum.linuxcnc.org/49-basic-configur...r-spindle-ccw#333214)
Some questions about that:
1. Do I have to connect /TX3BENA and /TX0BENA with i/0 pins and config them to low in the .hal file?
2. Can I pull /TX3BENA and /TX0BENA low to GND to save I/O ports?
3. What reason only Differential outputs TX0B and TX3B can be Tristated, do they have a special purpose?
4. Is ENCMUX managed by the 6i25 or do I have to handle the mux things in the .hal myself?
There are a few more questions but this is enough for today.
(my configuration so far was in www.forum.linuxcnc.org/49-basic-configur...r-spindle-ccw#333214)
Conn
P2 INTERNAL FUNCTION
DIR 7I52S HDR50 7I52S HDR50 6I25 HDR26 6I25 .vhd „virtual DB
in /TX3BENA 1 1 IO17 IOPortTag & x"00" & NullTag & x"00", -- I/O 00
GND 2
out MENCA0 (Enc0 A) 3 2 IO18 IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 01
GND 4
out MENCB0 (Enc0 B) 5 3 IO19 IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 02
GND 6
out MIDX0 (Enc0 Index) 7 4 IO20 IOPortTag & x"00" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 03
GND 8
out MENCA1 (Enc1 A) 9 5 IO21 IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 04
GND 10
out MENCB1 (Enc1 B) 11 6 IO22 IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 05
GND 12
out MIDX1 (Enc1 Index) 13 7 IO23 IOPortTag & x"01" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 06
GND 14
out MENCA2 (Enc2 A) 15 8 IO24 IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 07
GND 16
out MENCB2 (Enc2 B) 17 9 IO25 IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 07
GND 18
out MIDX2 (Enc2 Index) 19 11 IO26 IOPortTag & x"02" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 09
GND 20
out ENCMUX 21 13 IO27 IOPortTag & x"00" & MuxedQCountSelTag & MuxedQCountSel0P-- I/O 10
GND 22
in TX5B 23 15 IO28 IOPortTag & x"05" & StepGenTag & x"81", -- I/O 11
GND 24
in TX5A 25 17 IO29 IOPortTag & x"05" & StepGenTag & x"82", -- I/O 12
GND 26
in TX4B 27 19 IO30 IOPortTag & x"04" & StepGenTag & x"81", -- I/O 13
GND 28
in TX4A 29 21 IO31 IOPortTag & x"04" & StepGenTag & x"82", -- I/O 14
GND 30
in TX3B 31 23 IO32 IOPortTag & x"03" & StepGenTag & x"81", -- I/O 15
GND 32
in TX3A 33
GND 34
in TX2B 35
GND 36
in TX2A 37
GND 38
in TX1B 39
GND 40
in TX1A 41
GND 42
in TX0B 43
GND 44
in TX0A 45
GND 46
in /TX0BENA 47 25 IO33 IOPortTag & x"00" & NullTag & x"00", -- I/O 16
GND 48
in +5V PWR 49 18 +5V BREAKOUT POWER OPTION +5V ?
GND 50 10 GND
/TX3BENA is an active low enable signal.
BREAKOUT POWER OPTION +5V DB25 pins 22,23,24 and 25
BREAKOUT POWER OPTION +5V HDR PINS 18,20,22,24,26
FIX GND HDR PINS 10,12,14,16
‘M’ prefix on the interface encoder signals is to
indicate that they are multiplexed signals.
Last edit: 14 Aug 2025 12:56 by juergen-home.
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- tommylight
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14 Aug 2025 13:12 #333414
by tommylight
Replied by tommylight on topic Connect Mesa 6i25 HDR26 with 7I52S HDR50
Moved to "driver boards".
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14 Aug 2025 14:30 #333416
by PCW
Replied by PCW on topic Connect Mesa 6i25 HDR26 with 7I52S HDR50
1. No, just ground them
2. See #1
3. Because the 7I52 (which supports RS-422/RS-485 Serial) and 7I52S use the same PCB
4. The FPGA source and HM2 driver support muxed encoders, so as long as the pinout file
is correct, there's nothing else needed
2. See #1
3. Because the 7I52 (which supports RS-422/RS-485 Serial) and 7I52S use the same PCB
4. The FPGA source and HM2 driver support muxed encoders, so as long as the pinout file
is correct, there's nothing else needed
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