Mesa 7i95

It works perfectly without error. Thanks to every body.

jurod wrote: It works perfectly without error. Thanks to every body.

Nice, glad it worked as i was not sure, but i thought i read about it so i was afraid of sending you into a goose chase!

Hello,
I just got a 7i95 and I'd like to replace 3 stepgen with 3 pwmgen, and use 3 encoders for closed loop.
I'm new to Mesa boards and I'm not sure how to achieve this.
I already took a look at PIN_7I95D_58.vhd, which I think is the file I need to edit but I couldn't find documentation for this.
Can you please tell me where to find docs to learn how to build the bitfile I need? Sorry if this has already been asked but I'm new to this and don't have much time to read the forum.

Thanks a lot.

Do you want 3 PWM gens replacing 3 stepgens on the 7I95 card?
DO you want PWM and DIR or PWM and ENA?

• Yes, in this case would be OK for me to loose 3 stepgens and get 3 pwmgens.
• I need PWM/DIR.

Here is a 7I95 configuration with the last 3 stepgens replaced with PWM/DIR
I have included the changed pinout source as an example if you want to build
/modify it yourself.
(you also need to include the new source file in the top level file to build it)

Hello

i was trying to modify the 7i95 configuration. I just wanted the last step/dir gen to be changed to a pwm/dir
But i have hard times installing Xilinx ISE Design suite. Could anyone maybe change the standard configuration so that the last steg/dir gen is a pwm/dir gen? or give me an alternative programm to edit.

thanks in advance.

7I95 config with PWM/DIR replacing STEP/DIR on last 7I95 STEPGEN connection:

Hi,
can you point me in the right direction how to control VFD with 7i95 board?
The vfd inputs: voltage 0-10v, frequency 0-100KHz and rs485

thank you

0 to 100 KHz could be generated by a Stepgen if one is free
What signal levels are needed for the 0 to 100KHz signal?