Emco PC Turn 55 retrofit

More
5 years 8 months ago #198042 by The Feral Engineer

rodw wrote: Peter, a very timely reminder that there is no need to chase latency down to the nth degree. Without a base thread, latency can be far higher than what many people are striving for. I think a lot of people get far to carried away reducing it.


Agreed. I had good results on my laptop with 65000, but the pi@200 with 50800 step per inch settings didn't care much for 75ipm rapids. The gearing on this lathe is wacky. 2.5:1 motor reduction, 2.5mm ball screws, 200 steps with 10 micro... Started getting flaky, so I dropped it to 130 and it's been better

Please Log in or Create an account to join the conversation.

More
5 years 8 months ago #198049 by PCW
Replied by PCW on topic Emco PC Turn 55 retrofit
Those issues are not likely to be latency related, even 100s of usec of latency
have negligible effect on the step generation and the maximum step rate is
complete unrelated to latency with Mesa cards.

If you have poor latency (but good enough to avoid real time errors)
You do need to have the DPLL setup and enabled to be able to generate
clean step signals.
The following user(s) said Thank You: Sadmeatball

Please Log in or Create an account to join the conversation.

More
5 years 8 months ago #198051 by The Feral Engineer

PCW wrote: Those issues are not likely to be latency related, even 100s of usec of latency
have negligible effect on the step generation and the maximum step rate is
complete unrelated to latency with Mesa cards.

If you have poor latency (but good enough to avoid real time errors)
You do need to have the DPLL setup and enabled to be able to generate
clean step signals.


How would I check this?

Please Log in or Create an account to join the conversation.

More
5 years 8 months ago #198220 by PCW
Replied by PCW on topic Emco PC Turn 55 retrofit

The Feral Engineer wrote:

PCW wrote: Those issues are not likely to be latency related, even 100s of usec of latency
have negligible effect on the step generation and the maximum step rate is
complete unrelated to latency with Mesa cards.

If you have poor latency (but good enough to avoid real time errors)
You do need to have the DPLL setup and enabled to be able to generate
clean step signals.


How would I check this?


You should have something like this in your hal file:

Code:
# latch 50 usec before nominal read time: setp hm2_7i76e.0.dpll.01.timer-us -50 # set timer 1 to 50 usec before read setp hm2_7i76e.0.stepgen.timer-number 1 # use timer 1 as sample time reference for all stepgens

Note if the latency is really bad you may have to increase the time to 100 usec or so
because of baseline drift.
The following user(s) said Thank You: The Feral Engineer

Please Log in or Create an account to join the conversation.

More
5 years 8 months ago - 5 years 8 months ago #198223 by The Feral Engineer
Thanks Peter

I'll check it out when I get back on the pi. I reconnected my laptop for my turret prove out. Pi is my endgame, but it's a pain in the rear with the keyboard and monitor sitting on top of the machine.
Last edit: 5 years 8 months ago by The Feral Engineer.

Please Log in or Create an account to join the conversation.

More
5 years 8 months ago #199221 by The Feral Engineer
I set the pi back up, have it hooked to an asus touch screen and I've been able to do some playing. I did an isolcpus = 2,3 and I have a better servo-thread jitter result than not having any isolcpus (130000 vs 280000 if I load chromium and start playing youtube videos). I have my servo timing set to 140000 in my ini file and as long as I don't use wifi with the machine enabled, it seems to run pretty reliably. If I try to surf the web and jog the machine, it isn't happy about it at all, which is fine.

I haven't tried the DPLL thing yet, I actually came on here to read up on how to do it and figured I'd give an update on it.

Please Log in or Create an account to join the conversation.

Time to create page: 0.066 seconds
Powered by Kunena Forum