Emco PC Turn 55 retrofit

PCW wrote:

Those issues are not likely to be latency related, even 100s of usec of latency
have negligible effect on the step generation and the maximum step rate is
complete unrelated to latency with Mesa cards.

If you have poor latency (but good enough to avoid real time errors)
You do need to have the DPLL setup and enabled to be able to generate
clean step signals.

Non-existant user wrote:

PCW wrote:

Those issues are not likely to be latency related, even 100s of usec of latency
have negligible effect on the step generation and the maximum step rate is
complete unrelated to latency with Mesa cards.

If you have poor latency (but good enough to avoid real time errors)
You do need to have the DPLL setup and enabled to be able to generate
clean step signals.

How would I check this?

# latch 50 usec before nominal read time:
setp hm2_7i76e.0.dpll.01.timer-us -50   # set timer 1 to 50 usec before read
setp hm2_7i76e.0.stepgen.timer-number 1 # use timer 1 as sample time reference for all stepgens