8i20/BLDC component, limited spindle speed

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16 Jul 2018 12:21 #114292 by blazini36

Which version of LinuxCNC are you using?


The nvqil should be the limit (according to the 8i20 manual).

I assumed that nvkqil=NVKQI based on it's default value and the fact that nvkqihi and nvkqilo exist but nvkqi does not.

nvqihi and nvqilo should be the high and low order halves of a long-int value. I don't actually recall _why_ they are split across two HAL parameters. The manual says that they are "ULONG" and the integer HAL pins are 32-bit (floats are 64-bit doubles)so it may be that I determined that they are a 64-bit value and had to spread across 2 32-bit pins.


So it looks like nvkqil=NVKQIL from the manual and it is the limit and nvkqilo, nvkqihi are part of NVKQI? That makes sense but I'm still not sure about the default value of the limit being lower than the split value of the gain. Then again some of this stuff is over my head.


Maybe PCW can advise?[/quote]

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16 Jul 2018 13:35 #114300 by PCW
Yeah ULONG to SSLBP is 32 bit, UINT is 16 bits so you should not change the "hi" parts and the "lo" parts have a unsigned 32 bit range

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16 Jul 2018 14:20 #114302 by andypugh
Is the split "correct" or could we combine them into a 32-bit HAL pin?

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16 Jul 2018 14:44 #114305 by PCW
A single u32 is correct

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16 Jul 2018 14:50 #114306 by andypugh

A single u32 is correct


Can you have a quick look at
github.com/LinuxCNC/linuxcnc/blob/master...tmot2/sserial.h#L227

And see how it needs to be corrected? (That's the virtual 8i20 discovery data)

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16 Jul 2018 15:04 #114309 by PCW
it looks like the lo/hi parts should just be merged (and use the low address)

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16 Jul 2018 17:46 #114321 by andypugh

it looks like the lo/hi parts should just be merged (and use the low address)


I will give that a try.

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16 Jul 2018 18:41 #114327 by blazini36
So I suppose in the meantime the changes I would likely want to make are:
nvkqilo-150000 as per manual
nvkqihi-leave at 0
nvkqil-200000 to be higher than nvkqilo?
the same adjustments for nvkdil,nkdilo and nvkdihi.

Andy, the changes that you are making to the 8i20 (driver?), how would they be released? Is it a compile a new branch kind of thing or is it something I can add to my current RIP?

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16 Jul 2018 18:57 #114331 by andypugh
If you have a RIP then you can just change the header file and recompile.

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17 Jul 2018 15:11 #114395 by blazini36

So I suppose in the meantime the changes I would likely want to make are:
nvkqilo-150000 as per manual
nvkqihi-leave at 0
nvkqil-200000 to be higher than nvkqilo?
the same adjustments for nvkdil,nkdilo and nvkdihi.

Andy, the changes that you are making to the 8i20 (driver?), how would they be released? Is it a compile a new branch kind of thing or is it something I can add to my current RIP?


I started to to make these changes last night but it didn't seem to be going well. nvkqil I could not get to set at 200000. Is there an internal limit for the value? It seemed as though I was just having issues with setserial again, but other parameters were setting easier.

PCW, can you confirm that the numbers I suggested above would be right? Any idea why my 8i20 would come with a default value of 32000 nvkqilo (NVKQI) when the manual suggests it be at 150000?

Andy, is there any way for setserial to run multiple "sets" at once?

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