6i24-25 and 7i52S

hi guys, i would like to use the combination from the headline.

but i couldn't find any firmware that matches the pinout with stepgen outputs.

I've tried and failed building one from the sources. actually building worked after some tweaks, but after flashing the card had to be recovered.

can anybody help me out with a bitfile?
thanks in advance!

What other I/O do you need or is a 7I52S on the first connector enough?

One 7i52S is enough its a very simple setup and i'm actually only using 2 encoders and 2 stepgens

thank you!

i guess i found the reason why my homebrew built didn't work. i compiled it for the wrong type (-16)... i will try again tomorrow but if you can provide a working bitfile it will be appreciated very much!

freeby.mesanet.com/5i24_25_svst6_6_7i52s.bit

thanks a lot! attached is my latest try. i will try both tomorrow at work!

using the sources from the git-master and Xilinx ISE 14.7.

just deleted my file, since it wasn't working. @pcw yours is working fine, thanks a lot

Hello,
Some questions about the syntax for writing pin.vhd files:

are these two modes of writing the same?

IOPortTag & x"00" & QCountTag & QCountQAPin,
IOPortTag & x"00" & QCountTag & QCountQBPin,
IOPortTag & x"00" & QCountTag & QCountIDXPin,
and
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"03",
or
IOPortTag & x"00" & StepGenTag & StepGenDirPin,
IOPortTag & x"00" & StepGenTag & StepGenStepPin,
and
IOPortTag & x"00" & StepGenTag & x"81",
IOPortTag & x"00" & StepGenTag & x"82",

And another question about the number of clocks we assign
to a pair of PWM / DIR outputs or a pair of outputs stepgen / dir
because I find an anomaly in these 2 files ?

PIN_SVSTSS6_4_8_7I52S_72 (4x stepgen and 2x pwm)
PWMTag, x"00", ClockHighTag, x"06",
StepGenTag, x"02", ClockLowTag, x"04",

PIN_SVSTSS6_4_8__7I52S_72 (6x stepgen)
PWMTag, x"00", ClockHighTag, x"06",

thank you !

1. Yes, the numeric constants are the same as the text constants (look at IDROMConst.vhd)

2. The tag after the clock tag is the number of instances of the module

Hello,
I am testing vhd file compilation (PIN_SVSS6_8_72) with ISE_14.7

I have 4 errors messages
with 5i24-25
which lines I still activate in TopPCIHostMot2.vhd please ?

ERROR:HDLCompiler:69 - "/home/ise/ise-projets/configs/hostmot2/source/hostmot2/TopPCIHostMot2.vhd"
Line 320: <std_logic_vector> is not declared.
Line 321: <std_logic_vector> is not declared.
Line 324: <std_logic_vector> is not declared.
Line 325: <std_logic_vector> is not declared.

Thank you