BSPI Questions and fanuc red cap digital drive questions

(Note to reader questions are after this introductory explanation)
Equipment Information:
Fanuc a06B-6089-H105 drive with abs encoder
5i24
7i44
7i46
7i42TA
Trinamic tmc 4672 pmsm FOC controller

Discussion:
I am retrofitting a redcap fanuc pmsm motor using the original digital drive and absolute encoders.
When I read around there are lots of questions on this and the answers always seem to say it is doable. But it seems something that has been doable for like 8 years but maybe not ever been done.
I think a lot of the difficulty is the FOC control really needs to be done in the FPGA but that requires some firmware that is not easy for most of us.

I am taking another approach, trinamic makes a pmsm foc controller ic that can be controlled via spi, analog or pwm, including passing shaft angle via spi. This chip is around 10 bucks and seems it will do everything needed as long as the drives are put into the type A interface (6 pwm lines for the high and low sides of the 3 phase bridge)

My plan is to use the mesa 7i44 with the Fanuc abs capability to decode the abs encoder.
Use a 7i46 to communicate with each of the trinamic chips to pass velocity commands and shaft position
I built a small board that has the correct connectors for the fanuc cables. (both encoder and drive - as they are separate on the type an interface, type b interface seems to use locked antiphase which it seems is not common among off the shelf foc controllers and also slightly more dangerous depending on if zero pwm would is an error to the drive or if that is full reverse)

The setup includes a bidirectional analog switch to connect the pwm pins on the dive to standard IO pins when drive ready is not asserted to allow for the reading of error conditions and when asserted it connects the pwm pins of the drive to the trinamic's outputs.


First I plan to pass the shaft position through a hal component via spi to the foc controller just to see if I can get things working. If that works I will either try to modify the firmware for the 5i24 to directly pass the decoded shaft position to the trinamic controller reducing the latency to an acceptable level or beg for help from someone more knowledgeable to assist with the change. My vhdl knowledge is minimal and there is a lot of undocumented excitement in the firmware. But I thought just constantly adding the shaft position to the bspi write queue shouldn't be insanely complicated (famous last words). Who knows passing the shaft position through hal may be fast enough.

This leads me to a couple questions:
1.)Can Anyone help with what exactly how to connect to the interface
With a type A interface (please see attached picture for interface specs)
The * next to the names PWMA-F I assume means active low. I also assume from things i have picked up on multiple posts that they need to be pulled low by open drain pwm pins? I am assuming the amplifier when not in error mode pulls the pins up to 5v, when it is in error mode do I need to provide pull ups for the error lines?
I am assuming they are 5v ttl levels

2.) since these 6 lines are the high and low sides to the 3 phase h bridge then it would seem two pieces of information are critical.
Which are which? I.e. is it PWMA-F = HIgh U, Low U, High V, Low V, High W, Low W. or is it PWMA-F = High U, High V, High W, Low U, Low V, Low W

3.) Does anyone have info on the deadband? I saw PCW post some info on the deadband for some of the older digital drives but not these. If that info is not available does anyone have an idea on how to empirically find this? (maybe by using a dummy load to look at switching times on a single-phase pair and leaving some headroom.

4.) I noticed the DBSPI tag exists but it seems the hal driver is incomplete for this.
I am a little confused on the Frame and CS pins for the BSPI driver.
Can the frame pin be ignored and just use the CS0-7 pins if I only have 3 devices and done mind using IO's
Why are there 8 CS pins if there are only 16 possible channels per BSPI?

5.) My device uses a 40bit datagram, the notes say this is workable but that special requirements will be needed. It seems part of this is the dont clear setting and then two descriptors a 32 and an 8. But how to go about executing these is elluding me.
Truthfully the entire scheme of read write allocate etc isnt fully clear. But using the code examples from the 7k65 and some other comps I have seen written I can probably figure out the basic version of 32bits or lesser but the 40 bit is really unclear.




Thanks so much for reading all of this! Any advice or help is greatly appreciated.

Its probably no big deal to add DBSPI support to the hostmot2 driver since its basically identical register wise, it just needs to work with either GTAG and setup the decoded
CS signals

BSPI assumes that an external decoder will be used to generate the CS signals so
only channel addresses are output on the CS pins. These need to be gated with the frame
signal to generate a proper CS. This gating and decoding would normally be done in the external decoder say a 74ACT138.

yes, but I am trying to use the fanuc amps, I guess if I need to I can go the replacement route. But it seems a doable project and love a challenge