custom mesa implementation

Hi everybody,

I am thinking about making my own mesa card, I want to make something like the 7i76e board using a Lattice FPGA,
first question: can I emulate it or some license from MESA prevent me from doing it?

I have seen this folder: github.com/LinuxCNC/hostmot2-firmware/blob/master/src/ .

The main modules I need are 2:
-one to control the motors given position, velocity, or acceleration(can be easily found online)
-one to talk via ethernet with the PC, I see the etherhm2.vhd and etherhm2.zip, can I use this modules to talk via ethernet?

Thanks to anyone who answer

All hostmot2 firmware is open source (Combined GPL and BSD) licensed, you can use it anyway you like.
I suspect you need to be rather dedicated to port the Hostmot2 VHDL to a non-Xilinx chip but the Machine Kit people have done this with a couple Lattice chips, though I don't think they have ported any host interface parts (like the Ethernet code listed above)

I have a 5i20 and wanted to write a bit file for it. I followed Tom-Itx's guide for spartan2 and
had problems with my custom .vhd . I decided to try to use an existing PIN-blah.vhd to be sure my install was good.
I chose PIN_SVST4_8_72.vhd and edited Top9030HostMot2.vhd . The edit only changed

--use work.i20card.all; -- needs 5i20.ucf and SP2 200K 208 pin
use work.i65card.all; -- needs 4i65.ucf and SP2 200K 208 pin
to:
use work.i20card.all; -- needs 5i20.ucf and SP2 200K 208 pin
--use work.i65card.all; -- needs 4i65.ucf and SP2 200K 208 pin

and changed
use work.PIN_SVSmithy_72.all;
--use work.PIN_SVST8_4IM2_72.all;
--use work.PIN_SVST8_4_72.all;
to
--use work.PIN_SVSmithy_72.all;
--use work.PIN_SVST8_4IM2_72.all;
use work.PIN_SVST8_4_72.all;

then i set
Synthese XST properties
to Speed, High, use Synthesis constraints
and applied
then dbl clicked on Generate Programming File
and got errors
1st error was
OutpuPinsPerModule was not in library
found it, added it, retried
got errors
GetModuleHint not in library
found it added it retried
got errors
a list of missing in library..
timestampd
cpdrive
inmuxd
inm
dpainterd
xfmrout

I can add all but dpaintedd, it doesnt exist on fresh install of Xilinx 9.2i and newest mesa files for 5i20

question..
should i use 9.2i per Tom's suggestion it's needed for Spartan2?
( i'm on Debian 3.4.55-4linuxcnc i686 )

should i be able to build a bitfile as described?

what to do about dpainterd?

Thanks TomP

reported in console frame:
ERROR:HDLParsers:709 - "/lib/firmware/mesa/5i20/CONFIGS/HOSTMOT2/SOURCE/hostmot2.vhd" Line 3285. dpainterd is not an entity name
ERROR:HDLParsers:709 - "/lib/firmware/mesa/5i20/CONFIGS/HOSTMOT2/SOURCE/hostmot2.vhd" Line 3318. dpainterd is not an entity name

Sorry, the 5I20 project file has not been updated in a while...

Entity dpainterd is in the vhd file dpainter.vhd, did you add dpainter.vhd to the source list?

PDW thanks,
I added dpainter.vhd and got these 2 errors
"""
Entity <dpainterd> compiled.
ERROR:HDLParsers:3352 - "/lib/firmware/mesa/5i20/CONFIGS/HOSTMOT2/SOURCE/dpainter.vhd" Line 121. Unconstrained array subtype indications (rateaccum) are not supported for alias declarations.
ERROR:HDLParsers:3352 - "/lib/firmware/mesa/5i20/CONFIGS/HOSTMOT2/SOURCE/dpainter.vhd" Line 147. Unconstrained array subtype indications (modereg1) are not supported for alias declarations.
-->
"""
looking at dpainter.vhd source now.

( sorry i saw dpainter.vhd before but decided against any creativity ,
tho i could have peeked inside to see the hidden gem )
tomp

PCW hello,
i think editing those 2 lines to the format

alias | alianame | std_logic_vector(somerange) is originalitem(anotherrange)
will allow it to compile,
tho this is just pattern recognition hacking on my part.

eg:
alias bitcount: std_logic_vector(asize-1 downto rsize) is rateaccum(asize-1 downto rsize);

and

alias offpwm: std_logic_vector(31 downto 24) is modereg1(31 downto 24);

will compile but i dont know the correct ranges

am i headed inthe right direction?

thx tomp

if you cherry pick some files from
freeby.mesanet.com/hostmot2.zip

you should be more up-to-date

The alias bug is ISE version specific and just noticed it a week or so ago and patched the source but did not post it yet

Peter, Thanks,
I see that was the right direction
( your changes to dpainter.vhd declarations bitcount and offpwm)
but I never would have known the ranges.

You are extremely responsive to our questions.
kudos!

tomp

PCW hello
I still cant build a bitfile

I "use work.PIN_SVST2_8_72.all;" in attempt to avoid introducing my own errors,

I add vhd files to library as 'not available' errors appear,
using the suggested new sources,

but end with
...
Compiling vhdl file "/home/tomp/Xilinx92i/mesaSources22nov2018/5i20/CONFIGS/HOSTMOT2/SOURCE/hostmot2/simpledsad.vhd" in Library work.
Entity <simpledsad> compiled.
ERROR:HDLParsers:1418 - "/home/tomp/Xilinx92i/mesaSources22nov2018/5i20/CONFIGS/HOSTMOT2/SOURCE/hostmot2/simpledsad.vhd" Line 119. Formal generic IBUF_LOW_PWR does not exist in IBUFDS.
-->
Process "Synthesize" failed

i cant find IBUF_LOW_PWR in any files
what to try?

thanks tomp

PCW
googling suggest this is something out ofthe newer Xilinx Vivaldo
should I just remove the line? ( sorry i didnt google it first )
thx tomp