ColorCNC Colorlight 5A-75E/5A-75B as FPGA controller board
16 May 2022 21:06 #243112
by TOLP2
Replied by TOLP2 on topic ColorCNC Colorlight 5A-75E/5A-75B as FPGA controller board
Small update:
While developing I found a few bugs which need to be resolved: when no GPIO, PWM or Stepgen is defined, the firmware crashes as it is trying to create a register with a width of 0. At this moment at least one of each have to be defined. When the encoder driver software is finished, I'll tackle this problem as well.
Another nice feat: I'm making a hat for the RV901T, so all the stepper drives, switches and user input can be connected easilty. This board also contains a FTDI232 chipset so it can be reprogrammed on the fly.
- the firmware is now supporting RV901T and the various ColorLight cards;
- the firmware is expanded with the support for encoders (up to 32
). This new module has a different layout then the previous layouts, making it faster and more concise to develop; - the target of this project is known: my Emco5 will become the test-bed for this firmware, an example of the config is given below. Have to say, it makes the configuration as easy as it can get.
{
"board_name": "test_PWM_GPIO",
"baseclass": "firmware.boards.RV901T",
"clock_frequency": 50000000,
"ethphy": {
"tx_delay": 0
},
"etherbone": {
"ip_address": "10.0.0.10",
"mac_address": "0x10e2d5000000"
},
"gpio_in": [
{
"name": "rapid_override_reset",
"pin":"J601:7"
},
{
"name": "feed_override_reset",
"pin":"J601:8"
},
{
"name": "spindle_override_reset",
"pin":"J601:9"
}
],
"gpio_out": [
{
"name": "rapid_override_active",
"pin":"J601:15"
},
{
"name": "feed_override_active",
"pin":"J601:16"
},
{
"name": "spindle_override_active",
"pin":"J601:17"
},
{
"name": "stepgen_shared_enable",
"pin":"J600:39"
}
],
"pwm": [
{
"name": "test_otherwise_no_compile",
"pin":"J601:36"
}
],
"stepgen": [
{
"name": "stepgen_0",
"step_pin": "J600:38",
"dir_pin": "J600:36",
"soft_stop": true
},
{
"name": "stepgen_1",
"step_pin": "J600:34",
"dir_pin": "J600:32",
"soft_stop": true
},
{
"name": "stepgen_2",
"step_pin": "J600:37",
"dir_pin": "J600:35",
"soft_stop": true
},
{
"name": "stepgen_3",
"step_pin": "J600:33",
"dir_pin": "J600:31",
"soft_stop": true
}
],
"encoders": [
{
"name": "rapid_override",
"pin_A": "J601:7",
"pin_B": "J601:8"
},
{
"name": "feed_override",
"pin_A": "J601:9",
"pin_B": "J601:10"
},
{
"name": "spindle_override",
"pin_A": "J601:11",
"pin_B": "J601:12"
},
{
"name": "MPG",
"pin_A": "J601:13",
"pin_B": "J601:14"
}
]
}While developing I found a few bugs which need to be resolved: when no GPIO, PWM or Stepgen is defined, the firmware crashes as it is trying to create a register with a width of 0. At this moment at least one of each have to be defined. When the encoder driver software is finished, I'll tackle this problem as well.
Another nice feat: I'm making a hat for the RV901T, so all the stepper drives, switches and user input can be connected easilty. This board also contains a FTDI232 chipset so it can be reprogrammed on the fly.
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19 May 2022 14:29 - 20 May 2022 21:33 #243347
by TOLP2
Replied by TOLP2 on topic ColorCNC Colorlight 5A-75E/5A-75B as FPGA controller board
Romanetz, can you please give some guidance how you managed to compile:
- which version of ISE did you use?
- did you only use the verilog code produced by Litex, or did you need any other file as well.
Would love to se a screenshot of your ISE environment.
Edit: after some tinkering I managed to compile the firmware for the board. Turns out Litex dumps some erronous clock constraints at the end of the file. I've deleted those lines and now it compiles. I can read the magic and reset the board. However, as soon as I start reading data from the board, it stops working
. Have made some changes to the firmware, so I have to cross-reference with the 5A-75E to see whether the problem is board specific or that I broke the firmware...
Edit 2: In the branch encoder I have now a working firmware and driver which supports the modules GPIO, PWM/PDM, stepgen en encoders. Now it is time to write down for everybody how to hook this thing up for their specific setup and perform some tests. I suck at soldering SMD, still have to test anything with inputs...
- which version of ISE did you use?
- did you only use the verilog code produced by Litex, or did you need any other file as well.
Would love to se a screenshot of your ISE environment.
Edit: after some tinkering I managed to compile the firmware for the board. Turns out Litex dumps some erronous clock constraints at the end of the file. I've deleted those lines and now it compiles. I can read the magic and reset the board. However, as soon as I start reading data from the board, it stops working
. Have made some changes to the firmware, so I have to cross-reference with the 5A-75E to see whether the problem is board specific or that I broke the firmware...Edit 2: In the branch encoder I have now a working firmware and driver which supports the modules GPIO, PWM/PDM, stepgen en encoders. Now it is time to write down for everybody how to hook this thing up for their specific setup and perform some tests. I suck at soldering SMD, still have to test anything with inputs...
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