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ColorCNC Colorlight 5A-75E/5A-75B as FPGA controller board
- meister
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1 year 2 months ago #333845
by meister
Replied by meister on topic ColorCNC Colorlight 5A-75E/5A-75B as FPGA controller board
minimal fpga project, just edit the pins file to match your pinout:
github.com/multigcs/FPGA-blinky/tree/main/Colorlight5A-75E
i can't remember but i think it was already for the v8.2 board
if it works, you can take a look here:
github.com/multigcs/riocore/tree/dev/rio...olorlight5A-75B-v8.0
github.com/multigcs/FPGA-blinky/tree/main/Colorlight5A-75E
i can't remember but i think it was already for the v8.2 board
if it works, you can take a look here:
github.com/multigcs/riocore/tree/dev/rio...olorlight5A-75B-v8.0
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- benn686
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1 year 2 months ago #334148
by benn686
Replied by benn686 on topic ColorCNC Colorlight 5A-75E/5A-75B as FPGA controller board
I found a few lpf files.. like the one litex generates, and the one here:
github.com/ZeroMips/Colorlight-5A-75B-gp.../master/gpiotest.lpf
However, when I program the bitstream, it doesn't seem to be doing anything. Even a simple led blink.
Opening the lpf in Lattice Diamond, I notice that these lpf files show errors in the spreadsheet view.. so I think Lattice is ignoring the pin assignments all together?
github.com/ZeroMips/Colorlight-5A-75B-gp.../master/gpiotest.lpf
However, when I program the bitstream, it doesn't seem to be doing anything. Even a simple led blink.
Opening the lpf in Lattice Diamond, I notice that these lpf files show errors in the spreadsheet view.. so I think Lattice is ignoring the pin assignments all together?
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7 months 1 week ago #344638
by jaae
Replied by jaae on topic ColorCNC Colorlight 5A-75E/5A-75B as FPGA controller board
A Week of Python Purgatory: My Colorlight 5A-75B Still Thinks It's a Paperweight!
The Config (JSON files): I’ve attached my current JSON setup (j1.jpg and j2.jpg). I’ve spent a week tweaking these pins for my 6-axis setup, but I’m not 100% sure if LiteXCNC likes how I’ve named things or if my GPIO mapping is actually valid for the v8.2 board.
The Environment: My pip list shows I’m in a clean venv with LiteX-2025.12.
Questions for the Pros:
JSON Review: Can someone look at my modules and instances in the attached JSON? Does the way I defined axis_x through axis_c look correct for a 6-axis machine?
Watchdog: Is my timeout: 10000000 in the JSON too high, or is it okay for a standard setup?
Buffer Chips (v8.2): Based on my GPIO pin choices in the JSON, will I run into trouble with the buffer chips on this v8.2 board when connecting to 5V drivers?
The Current Setup:
OS: Debian 12 (Bookworm) with a Python Virtual Environment. (Debian is no longer silently judging me, but my Mini PC is).
Board: Colorlight 5A-75B v8.2.
Toolchain: Yosys and Nextpnr-ecp5 are installed.
Goal: A 6-axis CNC beast, controlled by Ethernet.
I have my pip list showing the full LiteX-2025.12 venv. Can someone please review my synthesis log to see why I am not generating a bitstream, even with yosys and nextpnr installed?
I’ve attached the evidence: my pip list, terminal outputs (json_1.png and json_2.png for the JSON files), and my which python3 output (proving I’m not crazy). Any advice from someone who’s survived a week in "Python Purgatory" would be amazing!
Thanks,
Jaae
The Config (JSON files): I’ve attached my current JSON setup (j1.jpg and j2.jpg). I’ve spent a week tweaking these pins for my 6-axis setup, but I’m not 100% sure if LiteXCNC likes how I’ve named things or if my GPIO mapping is actually valid for the v8.2 board.
The Environment: My pip list shows I’m in a clean venv with LiteX-2025.12.
Questions for the Pros:
JSON Review: Can someone look at my modules and instances in the attached JSON? Does the way I defined axis_x through axis_c look correct for a 6-axis machine?
Watchdog: Is my timeout: 10000000 in the JSON too high, or is it okay for a standard setup?
Buffer Chips (v8.2): Based on my GPIO pin choices in the JSON, will I run into trouble with the buffer chips on this v8.2 board when connecting to 5V drivers?
The Current Setup:
OS: Debian 12 (Bookworm) with a Python Virtual Environment. (Debian is no longer silently judging me, but my Mini PC is).
Board: Colorlight 5A-75B v8.2.
Toolchain: Yosys and Nextpnr-ecp5 are installed.
Goal: A 6-axis CNC beast, controlled by Ethernet.
I have my pip list showing the full LiteX-2025.12 venv. Can someone please review my synthesis log to see why I am not generating a bitstream, even with yosys and nextpnr installed?
I’ve attached the evidence: my pip list, terminal outputs (json_1.png and json_2.png for the JSON files), and my which python3 output (proving I’m not crazy). Any advice from someone who’s survived a week in "Python Purgatory" would be amazing!
Thanks,
Jaae
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- d12k6
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3 months 1 week ago - 3 months 1 week ago #347892
by d12k6
Replied by d12k6 on topic ColorCNC Colorlight 5A-75E/5A-75B as FPGA controller board
Hello all,
I’ve been struggling for about two weeks to flash a bitstream onto my Colorlight board (V8.2) using an external Adafruit FT232H USB-to-GPIO/SPI/I2C board, but I keep running into JTAG initialization and IDCODE errors.
I'm hoping someone here might spot what I am missing in my setup. Here are the details of my configuration and what I've observed so far:
Commands:
Questions:
Has anyone successfully used an Adafruit FT232H to flash a Colorlight V8.2 board via JTAG?
To completely rule out any issues with my current .bit file (or potential synthesis/mapping mismatches), does anyone happen to have a known-working, minimal test bitstream (e.g., a simple blinky for the ECP5 LFE5U-25F / Colorlight 5A-75B) that I could use just to verify that the flash programming and execution works?Any advice or working command configurations would be greatly appreciated!
Thanks
I'm hoping someone here might spot what I am missing in my setup. Here are the details of my configuration and what I've observed so far:
- FT232H D0(TCK) - Colorlight TCK J27
- FT232H D1(TDI) - Colorlight TDI J32
- FT232H D2(TDO) - Colorlight TDO J30
- FT232H D3(TMS) - Colorlight TMS J31
- GND - Colorlight J34 (3V3 is not connected)
Commands:
Code:
sudo /opt/oss-cad-suite/bin/openFPGALoader -c ft232 --fpga-part LFE5U-25F --freq 100000 --write-flash /home/cnc/Desktop/LiteCNC/colorlight_pins/gateware/colorlight_5a_75b.bit
write to flash
Can't read iSerialNumber field from FTDI: considered as empty string
Jtag frequency : requested 100.00KHz -> real 100.00KHz
Open file DONE
Parse file b3bdffff DONE
mismatch between target's idcode and bitstream idcode bitstream has 0x41111043 hardware requires 0xf819bfff
Error: Failed to program FPGA: std::exception
Questions:
Has anyone successfully used an Adafruit FT232H to flash a Colorlight V8.2 board via JTAG?
To completely rule out any issues with my current .bit file (or potential synthesis/mapping mismatches), does anyone happen to have a known-working, minimal test bitstream (e.g., a simple blinky for the ECP5 LFE5U-25F / Colorlight 5A-75B) that I could use just to verify that the flash programming and execution works?Any advice or working command configurations would be greatly appreciated!
Thanks
Last edit: 3 months 1 week ago by d12k6.
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- romanetz
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2 months 1 hour ago #349173
by romanetz
Replied by romanetz on topic ColorCNC Colorlight 5A-75E/5A-75B as FPGA controller board
I'd like to share some latest information regarding current status of the project.
Support of serial port (with almost the same principle as pktuart) has been added in last pull request. Yet not approved by Peter. github.com/Peter-van-Tol/LiteX-CNC/pull/155
Support of serial port (with almost the same principle as pktuart) has been added in last pull request. Yet not approved by Peter. github.com/Peter-van-Tol/LiteX-CNC/pull/155
The following user(s) said Thank You: rodw, kaya
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2 weeks 6 days ago #350199
by romanetz
Replied by romanetz on topic ColorCNC Colorlight 5A-75E/5A-75B as FPGA controller board
Hi everyone, I wanted to share my progress on developing an EtherCAT slave for the Colorlight 5A-75E board integrated with LiteXCNC, and hopefully get some advice from the community.The basic skeleton of the firmware is ready. The board is alive and successfully responding to the master's initial requests—the physical layer and core logic are up and running. Right now, I am focusing on debugging the SII EEPROM emulation. As soon as board gets to PREOP/OP state, I will share further updates.
The following user(s) said Thank You: besriworld, wodrak, NWE
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