Mesa 7i96s a little jitter

Yes but I don’t have them right now. I do know that there is no mention of dpll in either hal or ini as I searched for it. I used pncconfig (which had the 7i96d option) and the 7i96s out of the box.

Yes, it looks like the pncconf 7I96S configuration is missing the DPLL setup.

Adding:

setp hm2_7i96s.0.dpll.01.timer-us -100
setp hm2_7i96s.0.stepgen.timer-number 1

to your hal file should fix it.

Great thanks PCW, I wish I’d tried this at the beginning but I went off down the intel Ethernet route just assuming it must be a difference with the 7i96s - anyway will try it out and report back.

Disabling IRQ coalescing should always be done with Intel MACs
as it lessens the likelyhood of a real time error

That fixed it - thankyou! So what does the dpll actually do? I read the mesa manual but couldn’t find anything.

The DPLL locks onto the nominal servo thread read time and
re-times the sampling  or writing of selected values
(step generator position, encoder position, galvanometer position  etc)
to remove host read or write latencies as a variable. Typically
read sample time variation can be reduced from 100s of usec
to about 250 ns. This is important because sampling jiitter
causes bogus following errors (and subsequent bogus corrections)

The DPLL is also used to start operations before the nominal read times
(like absolute encoder transfers) so the data is available at the nominal read
time without busywaiting.