with only 10 outputs on J600/J601. There are 2 more available via JP4, but 12 is still far from 24. So you either have to modify the board or use 2 stock boards.
Not 16 ?
I read that there are 10 outputs on J600 or J601 and 6 on the JP4, two buffered and four unbuffered.
I can't test this outputs, because I can't compile your code.
I got this :
root@HP-15s:~/litehm2-master# ./litehm2.py
INFO:S6PLL:Creating S6PLL, speedgrade -2.
INFO:S6PLL:Registering Single Ended ClkIn of 25.00MHz.
INFO:S6PLL:Creating ClkOut0 sys of 100.00MHz (+-10000.00ppm).
INFO:S6PLL:Creating ClkOut1 fast of 200.00MHz (+-10000.00ppm).
Traceback (most recent call last):
File "/root/litehm2-master/./litehm2.py", line 178, in <module>
main()
File "/root/litehm2-master/./litehm2.py", line 159, in main
soc = LiteHM2(ip_address=args.ip_address,
File "/root/litehm2-master/./litehm2.py", line 78, in __init__
main_ram_init = get_mem_data("firmware/firmware.bin",
TypeError: get_mem_data() got an unexpected keyword argument 'data_width'
After removing line containing "data with" :
root@HP-15s:~/litehm2-master#
./litehm2.py
INFO:S6PLL:Creating S6PLL, speedgrade -2.
INFO:S6PLL:Registering Single Ended ClkIn of 25.00MHz.
INFO:S6PLL:Creating ClkOut0 sys of 100.00MHz (+-10000.00ppm).
INFO:S6PLL:Creating ClkOut1 fast of 200.00MHz (+-10000.00ppm).
INFO:SoC: __ _ __ _ __
INFO:SoC: / / (_) /____ | |/_/
INFO:SoC: / /__/ / __/ -_)> <
INFO:SoC: /____/_/\__/\__/_/|_|
INFO:SoC: Build your hardware, easily!
INFO:SoC:
INFO:SoC:Creating SoC... (2023-05-29 19:46:58)
INFO:SoC:
INFO:SoC:FPGA device : xc6slx16-2-ftg256.
INFO:SoC:System clock: 100.000MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:
INFO:SoC:Initial SoC:
INFO:SoC:
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:
INFO:SoC:Controller ctrl added.
INFO:SoC:CPU vexriscv added.
INFO:SoC:CPU vexriscv adding IO Region 0 at 0x80000000 (Size: 0x80000000).
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False.
INFO:SoC:CPU vexriscv overriding sram mapping from 0x01000000 to 0x10000000.
INFO:SoC:CPU vexriscv setting reset address to 0x00000000.
INFO:SoC:CPU vexriscv adding Bus Master(s).
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
INFO:SoC:CPU vexriscv adding Interrupt(s).
INFO:SoC:CPU vexriscv adding SoC components.
INFO:SoCRegion:Region size rounded internally from 0x00000d38 to 0x00001000.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00000d38, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00000d38, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x10000000, Size: 0x00001000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x10000000, Size: 0x00001000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:main_ram Region added at Origin: 0x40000000, Size: 0x00004000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:main_ram added as Bus Slave.
INFO:SoC:RAM main_ram added Origin: 0x40000000, Size: 0x00004000, Mode: RW, Cached: True Linker: False.
INFO:SoCIRQHandler:uart IRQ allocated at Location 0.
INFO:SoCIRQHandler:timer0 IRQ allocated at Location 1.
Traceback (most recent call last):
File "/root/litehm2-master/./litehm2.py", line 178, in <module>
main()
File "/root/litehm2-master/./litehm2.py", line 159, in main
soc = LiteHM2(ip_address=args.ip_address,
File "/root/litehm2-master/./litehm2.py", line 119, in __init__
self.add_ethernet(
File "/opt/litex/litex/litex/soc/integration/soc.py", line 1538, in add_ethernet
ethmac = LiteEthMAC(
File "/opt/litex/liteeth/liteeth/mac/__init__.py", line 52, in __init__
wishbone_interface = LiteEthMACWishboneInterface(
File "/opt/litex/liteeth/liteeth/mac/wishbone.py", line 45, in __init__
mem_or_size = self.sram.reader.mems[n],
IndexError: list index out of range
I don't know what I'm doing wrong.
Could you write how to compile your code ?
