New project, litehm2: a hostmot2 port to linsn rv901t

root@HP-15s:~/litehm2-master# make
make -f Makefile.target TARGET=rv901t
make[1]: Wejście do katalogu '/root/litehm2-master'
dd if=/dev/zero of=build/rv901t/firmware/firmware.bin bs=32k count=1
1+0 przeczytanych rekordów
1+0 zapisanych rekordów
skopiowane 32768 bajtów (33 kB, 32 KiB), 0,000342593 s, 95,6 MB/s
dd if=/dev/zero of=build/rv901t/firmware/loader.bin bs=4k count=1
1+0 przeczytanych rekordów
1+0 zapisanych rekordów
skopiowane 4096 bajtów (4,1 kB, 4,0 KiB), 0,000228353 s, 17,9 MB/s
./litehm2.py --builddir=build/rv901t --config=configs/rv901t.conf
INFO:S6PLL:Creating S6PLL, speedgrade -2.
INFO:S6PLL:Registering Single Ended ClkIn of 25.00MHz.
INFO:S6PLL:Creating ClkOut0 sys of 100.00MHz (+-10000.00ppm).
INFO:S6PLL:Creating ClkOut1 fast of 200.00MHz (+-10000.00ppm).
INFO:SoC:        __   _ __      _  __  
INFO:SoC:       / /  (_) /____ | |/_/  
INFO:SoC:      / /__/ / __/ -_)>  <    
INFO:SoC:     /____/_/\__/\__/_/|_|  
INFO:SoC:  Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2023-05-30 20:22:40)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : xc6slx16-2-ftg256.
INFO:SoC:System clock: 100.000MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Controller ctrl added.
INFO:SoC:CPU vexriscv added.
INFO:SoC:CPU vexriscv adding IO Region 0 at 0x80000000 (Size: 0x80000000).
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False.
INFO:SoC:CPU vexriscv overriding sram mapping from 0x01000000 to 0x10000000.
INFO:SoC:CPU vexriscv setting reset address to 0x00000000.
INFO:SoC:CPU vexriscv adding Bus Master(s).
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
INFO:SoC:CPU vexriscv adding Interrupt(s).
INFO:SoC:CPU vexriscv adding SoC components.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00001000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00001000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x10000000, Size: 0x00001000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x10000000, Size: 0x00001000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:main_ram Region added at Origin: 0x40000000, Size: 0x00004000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:main_ram added as Bus Slave.
INFO:SoC:RAM main_ram added Origin: 0x40000000, Size: 0x00004000, Mode: RW, Cached: True Linker: False.
INFO:SoCIRQHandler:uart IRQ allocated at Location 0.
INFO:SoCIRQHandler:timer0 IRQ allocated at Location 1.
INFO:SoCRegion:Region size rounded internally from 0x00005000 to 0x00008000.
INFO:SoCBusHandler:Allocating IO Region of size 0x00005000...
ERROR:SoCBusHandler:Not enough Address Space to allocate Region.
make[1]: *** [Makefile.target:10: litehm2] Błąd 1
make[1]: Opuszczenie katalogu '/root/litehm2-master'
make: *** [Makefile:8: bitstreams/rv901t.bit] Błąd 2

diff -Naur old/opt/litex/litex-boards/litex_boards/platforms/linsn_rv901t.py new/opt/litex/litex-boards/litex_boards/platforms/linsn_rv901t.py
--- old/opt/litex/litex-boards/litex_boards/platforms/linsn_rv901t.py<->2023-05-30 21:05:02.018074388 +0200
+++ new/opt/litex/litex-boards/litex_boards/platforms/linsn_rv901t.py<->2023-05-30 21:26:10.730300504 +0200
@@ -54,6 +54,16 @@
         IOStandard("LVCMOS33")
     ),
.
+    # SPIFlash (W25Q32JV)
+    ("spiflash", 0,
+        # clk
+        Subsignal("cs_n", Pins("T3")),
+        Subsignal("clk",  Pins("R11")),
+        Subsignal("mosi", Pins("T10")),
+        Subsignal("miso", Pins("P10")),
+        IOStandard("LVCMOS33"),
+    ),
+
     # SDR SDRAM
     ("sdram_clock", 0, Pins("K11"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
     ("sdram_clock", 1, Pins("K12"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
@@ -82,6 +92,19 @@
 # Connectors ---------------------------------------------------------------------------------------
.
 _connectors = [
+    # Near Molex, two rows, ten pins, described as DOT.
+    ("JP4", {
+        # Buffered through U610 chan 0
+        7: "F12",
+        # Buffered through U610 chan 1
+        8: "F6",
+        # Unbuffered !!!
+#        3: "H5",
+        4: "G5",
+#        5: "G6",
+        6: "F5"
+    }),
+
     # Lower connector on board. Pin 1 marked with silkscreen layer, pins then
     # alternating through the two rows of the connector.
     ("J600", {