New project, litehm2: a hostmot2 port to linsn rv901t

Great Project.
How much trubble can be to add more cards like one i have in stock 5A-75E??

Can you specify a bit more which parts you have trouble with? Building the firmware is still a bit involved, but I can provide you with a bitstream once you specify which functions you need.

From the hardware side there are 3 main hurdles:
1) Changing some drivers from input to output (optional)
2) Getting the initial firmware flashed
3) Building a breakout board.

I would suggest you start with 2). Once you get that running you have a baseline to build upon.

Pro_El wrote:

How much trubble can be to add more cards like one i have in stock 5A-75E??
 

The biggest problem is to get the hostmot2 code to synthesize with a different tool, yosys for example. It has a reduced feature set compared to xilinx ISE. I started the work a while ago and am working on it from time to time. I have a 5A-75B to test with.

sensille wrote:

Building the firmware is still a bit involved, but I can provide you with a bitstream once you specify which functions you need.
 

Hi.
In my opinion, the most desirable bitstream is as described below.
1. Most people interested in this (or familiar projects) can't soldering SSOT packages with 0.64 mm spacing, so RV901T is better solution than Colorlight 75 series with no inputs at all (in factory state.)
2. If we  will assume RV901T with no modifications, we get only 24 outputs. It is enough (compare with LPT port), but we can't waste any, for example fo differential outputs (this we can with external circuits).
3. Most popular milling machines have four axes (X,Y,Z and rotary).
4. Lathe should have spindle encoder for threading (especially for rigid tapping, not available in competitive close to Linuxcnc).
5. Spindle should have PWM for speed regulation, and two enables (M3/M4).
6. Motors enable signal should be shared for pins savings.
In conclusion: 4 stepgen, 1 PWM, 1 motor enable, 2 spindle control, 2 mist and flood, 2 probe (tool lenght probe and 3d probe, but these may have different type of output, NC and NO, or PNP and NPN), )in sum 16 outputs.
Maybe second PWM is a good idea (for example for flood pump, or another device).
We still have 8 outputs to use, if no idea, let configure as universal outputs.
I have no tool changer, and have no experience what will be best for it, but it is worth giving something for this purpose.
About inputs, we have more than we need.
I suggest at least 2 encoders, one for spindle, second give possibility of nice and usefull control panel (encoder for jog).
Of course we need inputs as home or e-stop, but these may be configured as universal inputs.
But here we have so many resources that we don't have to save.
 

tuxcnc wrote:

sensille wrote:

Building the firmware is still a bit involved, but I can provide you with a bitstream once you specify which functions you need.
 
Hi.
In my opinion, the most desirable bitstream is as described below.
1. Most people interested in this (or familiar projects) can't soldering SSOT packages with 0.64 mm spacing, so RV901T is better solution than Colorlight 75 series with no inputs at all (in factory state.)
2. If we  will assume RV901T with no modifications, we get only 24 outputs. It is enough (compare with LPT port), but we can't waste any, for example fo differential outputs (this we can with external circuits).
3. Most popular milling machines have four axes (X,Y,Z and rotary).
4. Lathe should have spindle encoder for threading (especially for rigid tapping, not available in competitive close to Linuxcnc).
5. Spindle should have PWM for speed regulation, and two enables (M3/M4).
6. Motors enable signal should be shared for pins savings.
In conclusion: 4 stepgen, 1 PWM, 1 motor enable, 2 spindle control, 2 mist and flood, 2 probe (tool lenght probe and 3d probe, but these may have different type of output, NC and NO, or PNP and NPN), )in sum 16 outputs.
Maybe second PWM is a good idea (for example for flood pump, or another device).
We still have 8 outputs to use, if no idea, let configure as universal outputs.
I have no tool changer, and have no experience what will be best for it, but it is worth giving something for this purpose.
About inputs, we have more than we need.
I suggest at least 2 encoders, one for spindle, second give possibility of nice and usefull control panel (encoder for jog).
Of course we need inputs as home or e-stop, but these may be configured as universal inputs.
But here we have so many resources that we don't have to save.

 

I can build such a bitstream. I just wanted to order a new rv901t to test it on, but unfortunately in the last few weeks the availability of those boards has shrunken quite dramatically, so it doesn't really have much of a future. There is a predecessor (which I own), but it has a different FPGA (chinese brand, quite underdocumented).
Regarding output configuration: Each pin can either be used as a special function pin like stepgen/pwm/... or as generic IO. The special function is coded into the bitstream, but switching to GPIO can be done at runtime from HAL. So it makes sense to assign a special function to each available output.

I ordered a new rv901t so I can test on an unmodified one.

I can build such a bitstream. I just wanted to order a new rv901t to test it on, but unfortunately in the last few weeks the availability of those boards has shrunken quite dramatically, so it doesn't really have much of a future. There is a predecessor (which I own), but it has a different FPGA (chinese brand, quite underdocumented).
Regarding output configuration: Each pin can either be used as a special function pin like stepgen/pwm/... or as generic IO. The special function is coded into the bitstream, but switching to GPIO can be done at runtime from HAL. So it makes sense to assign a special function to each available output.

I tried to build that bitstream, but unfortunately you end up with only 10 outputs on J600/J601. There are 2 more available via JP4, but 12 is still far from 24. So you either have to modify the board or use 2 stock boards.

tuxcnc wrote:

Hi.
In my opinion, the most desirable bitstream is as described below.
1. Most people interested in this (or familiar projects) can't soldering SSOT packages with 0.64 mm spacing, so RV901T is better solution than Colorlight 75 series with no inputs at all (in factory state.)
2. If we  will assume RV901T with no modifications, we get only 24 outputs. It is enough (compare with LPT port), but we can't waste any, for example fo differential outputs (this we can with external circuits).

Hi
In  fact the modification of these boards is not so difficult. 
In case of RV901T you should cut one trace in two places then solder it to GND and add a smd 0805 1k resistor to 3V3. In the end you will get U603, U607, U602, U606 as input and U605, U601, U604, U600 as output ports.
In case of Colorlight 5A-75E the modification is a bit complicated but you do not need to solder chips completely. You should unsolder 2 pins of a group of ICs and solder them together by means of a couple of long jumper wires, then you need to solder those jumper wires to GND and 3V3

sensille wrote:

with only 10 outputs on J600/J601. There are 2 more available via JP4, but 12 is still far from 24. So you either have to modify the board or use 2 stock boards.

Not 16 ?
I read that there are 10 outputs on J600 or J601 and 6 on the JP4, two buffered and four unbuffered.
I can't test this outputs, because I can't compile your code.
I got this :

root@HP-15s:~/litehm2-master# ./litehm2.py
INFO:S6PLL:Creating S6PLL, speedgrade -2.
INFO:S6PLL:Registering Single Ended ClkIn of 25.00MHz.
INFO:S6PLL:Creating ClkOut0 sys of 100.00MHz (+-10000.00ppm).
INFO:S6PLL:Creating ClkOut1 fast of 200.00MHz (+-10000.00ppm).
Traceback (most recent call last):
  File "/root/litehm2-master/./litehm2.py", line 178, in <module>
    main()
  File "/root/litehm2-master/./litehm2.py", line 159, in main
    soc = LiteHM2(ip_address=args.ip_address,
  File "/root/litehm2-master/./litehm2.py", line 78, in __init__
    main_ram_init = get_mem_data("firmware/firmware.bin",
TypeError: get_mem_data() got an unexpected keyword argument 'data_width'

After removing line containing "data with" :

root@HP-15s:~/litehm2-master#
./litehm2.py
INFO:S6PLL:Creating S6PLL, speedgrade -2.
INFO:S6PLL:Registering Single Ended ClkIn of 25.00MHz.
INFO:S6PLL:Creating ClkOut0 sys of 100.00MHz (+-10000.00ppm).
INFO:S6PLL:Creating ClkOut1 fast of 200.00MHz (+-10000.00ppm).
INFO:SoC:        __   _ __      _  __  
INFO:SoC:       / /  (_) /____ | |/_/  
INFO:SoC:      / /__/ / __/ -_)>  <    
INFO:SoC:     /____/_/\__/\__/_/|_|  
INFO:SoC:  Build your hardware, easily!
INFO:SoC:

---

INFO:SoC:Creating SoC... (2023-05-29 19:46:58)
INFO:SoC:

---

INFO:SoC:FPGA device : xc6slx16-2-ftg256.
INFO:SoC:System clock: 100.000MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:

---

INFO:SoC:Initial SoC:
INFO:SoC:

---

INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:

---

INFO:SoC:Controller ctrl added.
INFO:SoC:CPU vexriscv added.
INFO:SoC:CPU vexriscv adding IO Region 0 at 0x80000000 (Size: 0x80000000).
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False.
INFO:SoC:CPU vexriscv overriding sram mapping from 0x01000000 to 0x10000000.
INFO:SoC:CPU vexriscv setting reset address to 0x00000000.
INFO:SoC:CPU vexriscv adding Bus Master(s).
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
INFO:SoC:CPU vexriscv adding Interrupt(s).
INFO:SoC:CPU vexriscv adding SoC components.
INFO:SoCRegion:Region size rounded internally from 0x00000d38 to 0x00001000.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00000d38, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00000d38, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x10000000, Size: 0x00001000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x10000000, Size: 0x00001000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:main_ram Region added at Origin: 0x40000000, Size: 0x00004000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:main_ram added as Bus Slave.
INFO:SoC:RAM main_ram added Origin: 0x40000000, Size: 0x00004000, Mode: RW, Cached: True Linker: False.
INFO:SoCIRQHandler:uart IRQ allocated at Location 0.
INFO:SoCIRQHandler:timer0 IRQ allocated at Location 1.
Traceback (most recent call last):
  File "/root/litehm2-master/./litehm2.py", line 178, in <module>
    main()
  File "/root/litehm2-master/./litehm2.py", line 159, in main
    soc = LiteHM2(ip_address=args.ip_address,
  File "/root/litehm2-master/./litehm2.py", line 119, in __init__
    self.add_ethernet(
  File "/opt/litex/litex/litex/soc/integration/soc.py", line 1538, in add_ethernet
    ethmac = LiteEthMAC(
  File "/opt/litex/liteeth/liteeth/mac/__init__.py", line 52, in __init__
    wishbone_interface = LiteEthMACWishboneInterface(
  File "/opt/litex/liteeth/liteeth/mac/wishbone.py", line 45, in __init__
    mem_or_size = self.sram.reader.mems[n],
IndexError: list index out of range
 

I don't know what I'm doing wrong.

Could you write how to compile your code ?

I fixed some bugs in the build process in the last couple of days. Are you on most recent master? Please note that although some patches are accepted, it still needs one more patch for litex-boards. I also updated the build instructions.

Let me know how it is going.