7i96s custom bitfile

Hmmmm still no luck.

Here is a quick vid of what happens...

www.youtube.com/shorts/XK0EZQOeCug

any ideas at all?...

Not sure but I would expect you would have to program a valid (meaning standard 7I96S)
configuration into the flash, power cycle and then restore the fallback configuration and
standard configurations via mesaflash to recover.

Is there a route to program the flash directly using fpga via jtag?

I thought that jtag only programs the fpga volatile memory, then using mesaflash the rom is programmed, unless I'm mistaken, which is quite likely !

I'll do some more digging too...

Sorry for taking up your time...

Yes, you can directly program the flash with the Efinity programmer
but it requires loading a JTAG --> SPI bridge configuration first
(the source is supplied in Efinity but you need to build it for the specific chip)

We avoid this with initial programming by JTAG loading the FPGA with normal
config and then using mesaflash to write the normal and fallback flash data
(mesaflash is about 20X faster at programming than Efinity)

Here is our complete init script:

. ~/efinity/2021.2/bin/setup.sh
efx_run.py seveni96s.xml --flow program --pgm_opts mode=jtag
echo "waiting for reset"
sleep 4
INTERFACE='elbp16'
IPADDR='192.168.1.121'
PROTOCOL='direct'
export INTERFACE
export IPADDR
export PROTOCOL
./setname 7I96S
./setmac 00601B168$1
./ereset
echo
echo "waiting for reset"
sleep 3
mesaflash --device 7i96s --addr 192.168.1.121 --write 7i96s_16m_fallback.bin --fallback
mesaflash --device 7i96s --addr 192.168.1.121 --write 7i96s_d.bin
./setipaddr 10 10 10 10
./getmask
./setmac

Thank you, as soon as I get a moment I'll give it a try.

For programming the fpga I'm using an ftdi ft4232,..remarkably hard to find a simple schematic amongst efinitys' documentation...lol..

Just want to say that once again your support has been outstanding.

Thank you.