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[Solved]How to enable/check MESA 7i96s with 7i76 daughter board - problem??

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16 Jun 2023 09:45 - 17 Jun 2023 07:00 #273687 by camb0
[Solved]How to enable/check MESA 7i96s with 7i76 daughter board - problem?? was created by camb0
Hi,
I've got my daughter board connected with a custom DB25->26 pin cable but I can't seem to talk to it.  I'm a bit suspect of the cable, this is the second one I;ve made.  I've tested the pins and they have connections and I'm pretty sure they're correct otherwise I'm pretty sure the pwr wouldn't work.
The 5V pwr LED is on, it's powered from the DB25 cable from the 26pin P1 expansion connection of the 7i96.  I've got field pwr (24v) to the TB1 field pwr, and the field pwr LED is lit (I know it's not needed).
I've flashed the 7i96s via MesaCT with 7i96s_7i76d.bin.
If I do a mesaflash read HMID it seems to only show the 7i96 pins.

I've tried to load it in HALRUN to see what it can see but I'm pretty sure I'm only seeing pins for the 7i96s as I would expect(hope) to see something like: hm2_7i96s.0.7i76.....
So I'm not sure if it's cable or a config issue.
I've looked at a post from PCW here, and I've read the man pages but I'm lost as to what the config string should look like (I've tried a few different variants from none to spelling out 3 of them to what's below).
Any tips on how to test my setup to isolate where I've missed something (or cable) would be appreciated.

halcmd: loadrt hostmot2
halcmd: loadrt hm2_eth board_ip="10.10.10.10 config="sserial_port_0=2"
halcmd: show pin
Owner   Type  Dir         Value  Name
    10  float IN            100  hm2_7i96s.0.dpll.01.timer-us
    10  float IN            100  hm2_7i96s.0.dpll.02.timer-us
    10  float IN            100  hm2_7i96s.0.dpll.03.timer-us
    10  float IN            100  hm2_7i96s.0.dpll.04.timer-us
    10  float IN             -1  hm2_7i96s.0.dpll.base-freq-khz
    10  u32   OUT    0x00000000  hm2_7i96s.0.dpll.ddsize
    10  float OUT             0  hm2_7i96s.0.dpll.phase-error-us
    10  u32   IN     0x00400000  hm2_7i96s.0.dpll.plimit
    10  u32   OUT    0x00000001  hm2_7i96s.0.dpll.prescale
    10  u32   IN     0x000007D0  hm2_7i96s.0.dpll.time-const
    10  s32   OUT             0  hm2_7i96s.0.encoder.00.count
    10  s32   OUT             0  hm2_7i96s.0.encoder.00.count-latched
    10  bit   I/O         FALSE  hm2_7i96s.0.encoder.00.index-enable
    10  bit   OUT          TRUE  hm2_7i96s.0.encoder.00.input-a
    10  bit   OUT         FALSE  hm2_7i96s.0.encoder.00.input-b
    10  bit   OUT          TRUE  hm2_7i96s.0.encoder.00.input-index
    10  bit   IN          FALSE  hm2_7i96s.0.encoder.00.latch-enable
    10  bit   IN          FALSE  hm2_7i96s.0.encoder.00.latch-polarity
    10  float OUT             0  hm2_7i96s.0.encoder.00.position
    10  float OUT             0  hm2_7i96s.0.encoder.00.position-latched
    10  bit   OUT         FALSE  hm2_7i96s.0.encoder.00.quad-error
    10  bit   IN          FALSE  hm2_7i96s.0.encoder.00.quad-error-enable
    10  s32   OUT             1  hm2_7i96s.0.encoder.00.rawcounts
    10  s32   OUT             1  hm2_7i96s.0.encoder.00.rawlatch
    10  bit   IN          FALSE  hm2_7i96s.0.encoder.00.reset
    10  float OUT             0  hm2_7i96s.0.encoder.00.velocity
    10  float OUT             0  hm2_7i96s.0.encoder.00.velocity-rpm
    10  s32   OUT             0  hm2_7i96s.0.encoder.01.count
    10  s32   OUT             0  hm2_7i96s.0.encoder.01.count-latched
    10  bit   I/O         FALSE  hm2_7i96s.0.encoder.01.index-enable
    10  bit   OUT         FALSE  hm2_7i96s.0.encoder.01.input-a
    10  bit   OUT         FALSE  hm2_7i96s.0.encoder.01.input-b
    10  bit   OUT          TRUE  hm2_7i96s.0.encoder.01.input-index
    10  bit   IN          FALSE  hm2_7i96s.0.encoder.01.latch-enable
    10  bit   IN          FALSE  hm2_7i96s.0.encoder.01.latch-polarity
    10  float OUT             0  hm2_7i96s.0.encoder.01.position
    10  float OUT             0  hm2_7i96s.0.encoder.01.position-latched
    10  bit   OUT         FALSE  hm2_7i96s.0.encoder.01.quad-error
    10  bit   IN          FALSE  hm2_7i96s.0.encoder.01.quad-error-enable
    10  s32   OUT             0  hm2_7i96s.0.encoder.01.rawcounts
    10  s32   OUT             0  hm2_7i96s.0.encoder.01.rawlatch
    10  bit   IN          FALSE  hm2_7i96s.0.encoder.01.reset
    10  float OUT             0  hm2_7i96s.0.encoder.01.velocity
    10  float OUT             0  hm2_7i96s.0.encoder.01.velocity-rpm
    10  bit   IN          FALSE  hm2_7i96s.0.encoder.hires-timestamp
    10  u32   IN     0x017D7840  hm2_7i96s.0.encoder.sample-frequency
    10  s32   IN             -1  hm2_7i96s.0.encoder.timer-number
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.000.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.000.in_not
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.001.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.001.in_not
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.002.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.002.in_not
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.003.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.003.in_not
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.004.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.004.in_not
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.005.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.005.in_not
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.006.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.006.in_not
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.007.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.007.in_not
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.008.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.008.in_not
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.009.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.009.in_not
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.010.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.010.in_not
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.011.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.011.in_not
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.012.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.012.in_not
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.013.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.013.in_not
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.014.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.014.in_not
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.015.in
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.015.in_not
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.016.in
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.016.in_not
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.017.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.017.in_not
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.018.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.018.in_not
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.019.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.019.in_not
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.020.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.020.in_not
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.021.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.021.in_not
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.022.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.022.in_not
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.023.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.023.in_not
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.024.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.024.in_not
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.025.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.025.in_not
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.026.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.026.in_not
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.027.in
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.027.in_not
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.028.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.028.in_not
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.029.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.029.in_not
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.030.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.030.in_not
    10  bit   IN          FALSE  hm2_7i96s.0.gpio.030.out
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.031.in
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.031.in_not
    10  bit   IN          FALSE  hm2_7i96s.0.gpio.031.out
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.032.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.032.in_not
    10  bit   IN          FALSE  hm2_7i96s.0.gpio.032.out
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.033.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.033.in_not
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.034.in
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.034.in_not
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.035.in
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.035.in_not
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.036.in
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.036.in_not
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.037.in
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.037.in_not
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.038.in
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.038.in_not
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.039.in
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.039.in_not
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.040.in
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.040.in_not
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.041.in
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.041.in_not
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.042.in
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.042.in_not
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.043.in
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.043.in_not
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.044.in
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.044.in_not
    10  bit   IN          FALSE  hm2_7i96s.0.gpio.044.out
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.045.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.045.in_not
    10  bit   IN          FALSE  hm2_7i96s.0.gpio.045.out
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.046.in
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.046.in_not
    10  bit   IN          FALSE  hm2_7i96s.0.gpio.046.out
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.047.in
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.047.in_not
    10  bit   IN          FALSE  hm2_7i96s.0.gpio.047.out
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.048.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.048.in_not
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.049.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.049.in_not
    10  bit   OUT         FALSE  hm2_7i96s.0.gpio.050.in
    10  bit   OUT          TRUE  hm2_7i96s.0.gpio.050.in_not
    10  s32   OUT             0  hm2_7i96s.0.inm.00.enc0-count
    10  s32   OUT             0  hm2_7i96s.0.inm.00.enc1-count
    10  s32   OUT             0  hm2_7i96s.0.inm.00.enc2-count
    10  s32   OUT             0  hm2_7i96s.0.inm.00.enc3-count
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.input-00
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.input-00-not
    10  bit   IN          FALSE  hm2_7i96s.0.inm.00.input-00-slow
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.input-01
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.input-01-not
    10  bit   IN          FALSE  hm2_7i96s.0.inm.00.input-01-slow
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.input-02
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.input-02-not
    10  bit   IN          FALSE  hm2_7i96s.0.inm.00.input-02-slow
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.input-03
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.input-03-not
    10  bit   IN          FALSE  hm2_7i96s.0.inm.00.input-03-slow
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.input-04
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.input-04-not
    10  bit   IN          FALSE  hm2_7i96s.0.inm.00.input-04-slow
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.input-05
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.input-05-not
    10  bit   IN          FALSE  hm2_7i96s.0.inm.00.input-05-slow
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.input-06
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.input-06-not
    10  bit   IN          FALSE  hm2_7i96s.0.inm.00.input-06-slow
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.input-07
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.input-07-not
    10  bit   IN          FALSE  hm2_7i96s.0.inm.00.input-07-slow
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.input-08
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.input-08-not
    10  bit   IN          FALSE  hm2_7i96s.0.inm.00.input-08-slow
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.input-09
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.input-09-not
    10  bit   IN          FALSE  hm2_7i96s.0.inm.00.input-09-slow
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.input-10
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.input-10-not
    10  bit   IN          FALSE  hm2_7i96s.0.inm.00.input-10-slow
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.raw-input-00
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.raw-input-00-not
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.raw-input-01
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.raw-input-01-not
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.raw-input-02
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.raw-input-02-not
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.raw-input-03
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.raw-input-03-not
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.raw-input-04
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.raw-input-04-not
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.raw-input-05
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.raw-input-05-not
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.raw-input-06
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.raw-input-06-not
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.raw-input-07
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.raw-input-07-not
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.raw-input-08
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.raw-input-08-not
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.raw-input-09
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.raw-input-09-not
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.raw-input-10
    10  bit   OUT         FALSE  hm2_7i96s.0.inm.00.raw-input-10-not
    10  bit   IN          FALSE  hm2_7i96s.0.led.CR01
    10  bit   IN          FALSE  hm2_7i96s.0.led.CR02
    10  bit   IN          FALSE  hm2_7i96s.0.led.CR03
    10  bit   IN          FALSE  hm2_7i96s.0.led.CR04
    10  bit   IN          FALSE  hm2_7i96s.0.outm.00.invert-04
    10  bit   IN          FALSE  hm2_7i96s.0.outm.00.invert-05
    10  bit   IN          FALSE  hm2_7i96s.0.outm.00.out-04
    10  bit   IN          FALSE  hm2_7i96s.0.outm.00.out-05
    10  bit   OUT         FALSE  hm2_7i96s.0.packet-error
    10  bit   OUT         FALSE  hm2_7i96s.0.packet-error-exceeded
    10  s32   OUT             0  hm2_7i96s.0.packet-error-level
    10  bit   IN          FALSE  hm2_7i96s.0.pwmgen.00.enable
    10  float IN              0  hm2_7i96s.0.pwmgen.00.value
    10  s32   OUT             0  hm2_7i96s.0.read-request.time
    10  s32   OUT             0  hm2_7i96s.0.read.time
    10  bit   IN          FALSE  hm2_7i96s.0.ssr.00.out-00
    10  bit   IN          FALSE  hm2_7i96s.0.ssr.00.out-01
    10  bit   IN          FALSE  hm2_7i96s.0.ssr.00.out-02
    10  bit   IN          FALSE  hm2_7i96s.0.ssr.00.out-03
    10  u32   IN     0x000F4240  hm2_7i96s.0.ssr.00.rate
    10  bit   IN          FALSE  hm2_7i96s.0.stepgen.00.control-type
    10  s32   OUT             0  hm2_7i96s.0.stepgen.00.counts
    10  float OUT             0  hm2_7i96s.0.stepgen.00.dbg_err_at_match
    10  float OUT             0  hm2_7i96s.0.stepgen.00.dbg_ff_vel
    10  float OUT             0  hm2_7i96s.0.stepgen.00.dbg_pos_minus_prev_cmd
    10  float OUT             0  hm2_7i96s.0.stepgen.00.dbg_s_to_match
    10  s32   OUT             0  hm2_7i96s.0.stepgen.00.dbg_step_rate
    10  float OUT             0  hm2_7i96s.0.stepgen.00.dbg_vel_error
    10  bit   IN          FALSE  hm2_7i96s.0.stepgen.00.enable
    10  float IN              0  hm2_7i96s.0.stepgen.00.position-cmd
    10  float OUT             0  hm2_7i96s.0.stepgen.00.position-fb
    10  float IN              0  hm2_7i96s.0.stepgen.00.velocity-cmd
    10  float OUT             0  hm2_7i96s.0.stepgen.00.velocity-fb
    10  bit   IN          FALSE  hm2_7i96s.0.stepgen.01.control-type
    10  s32   OUT             0  hm2_7i96s.0.stepgen.01.counts
    10  float OUT             0  hm2_7i96s.0.stepgen.01.dbg_err_at_match
    10  float OUT             0  hm2_7i96s.0.stepgen.01.dbg_ff_vel
    10  float OUT             0  hm2_7i96s.0.stepgen.01.dbg_pos_minus_prev_cmd
    10  float OUT             0  hm2_7i96s.0.stepgen.01.dbg_s_to_match
    10  s32   OUT             0  hm2_7i96s.0.stepgen.01.dbg_step_rate
    10  float OUT             0  hm2_7i96s.0.stepgen.01.dbg_vel_error
    10  bit   IN          FALSE  hm2_7i96s.0.stepgen.01.enable
    10  float IN              0  hm2_7i96s.0.stepgen.01.position-cmd
    10  float OUT             0  hm2_7i96s.0.stepgen.01.position-fb
    10  float IN              0  hm2_7i96s.0.stepgen.01.velocity-cmd
    10  float OUT             0  hm2_7i96s.0.stepgen.01.velocity-fb
    10  bit   IN          FALSE  hm2_7i96s.0.stepgen.02.control-type
    10  s32   OUT             0  hm2_7i96s.0.stepgen.02.counts
    10  float OUT             0  hm2_7i96s.0.stepgen.02.dbg_err_at_match
    10  float OUT             0  hm2_7i96s.0.stepgen.02.dbg_ff_vel
    10  float OUT             0  hm2_7i96s.0.stepgen.02.dbg_pos_minus_prev_cmd
    10  float OUT             0  hm2_7i96s.0.stepgen.02.dbg_s_to_match
    10  s32   OUT             0  hm2_7i96s.0.stepgen.02.dbg_step_rate
    10  float OUT             0  hm2_7i96s.0.stepgen.02.dbg_vel_error
    10  bit   IN          FALSE  hm2_7i96s.0.stepgen.02.enable
    10  float IN              0  hm2_7i96s.0.stepgen.02.position-cmd
    10  float OUT             0  hm2_7i96s.0.stepgen.02.position-fb
    10  float IN              0  hm2_7i96s.0.stepgen.02.velocity-cmd
    10  float OUT             0  hm2_7i96s.0.stepgen.02.velocity-fb
    10  bit   IN          FALSE  hm2_7i96s.0.stepgen.03.control-type
    10  s32   OUT             0  hm2_7i96s.0.stepgen.03.counts
    10  float OUT             0  hm2_7i96s.0.stepgen.03.dbg_err_at_match
    10  float OUT             0  hm2_7i96s.0.stepgen.03.dbg_ff_vel
    10  float OUT             0  hm2_7i96s.0.stepgen.03.dbg_pos_minus_prev_cmd
    10  float OUT             0  hm2_7i96s.0.stepgen.03.dbg_s_to_match
    10  s32   OUT             0  hm2_7i96s.0.stepgen.03.dbg_step_rate
    10  float OUT             0  hm2_7i96s.0.stepgen.03.dbg_vel_error
    10  bit   IN          FALSE  hm2_7i96s.0.stepgen.03.enable
    10  float IN              0  hm2_7i96s.0.stepgen.03.position-cmd
    10  float OUT             0  hm2_7i96s.0.stepgen.03.position-fb
    10  float IN              0  hm2_7i96s.0.stepgen.03.velocity-cmd
    10  float OUT             0  hm2_7i96s.0.stepgen.03.velocity-fb
    10  bit   IN          FALSE  hm2_7i96s.0.stepgen.04.control-type
    10  s32   OUT             0  hm2_7i96s.0.stepgen.04.counts
    10  float OUT             0  hm2_7i96s.0.stepgen.04.dbg_err_at_match
    10  float OUT             0  hm2_7i96s.0.stepgen.04.dbg_ff_vel
    10  float OUT             0  hm2_7i96s.0.stepgen.04.dbg_pos_minus_prev_cmd
    10  float OUT             0  hm2_7i96s.0.stepgen.04.dbg_s_to_match
    10  s32   OUT             0  hm2_7i96s.0.stepgen.04.dbg_step_rate
    10  float OUT             0  hm2_7i96s.0.stepgen.04.dbg_vel_error
    10  bit   IN          FALSE  hm2_7i96s.0.stepgen.04.enable
    10  float IN              0  hm2_7i96s.0.stepgen.04.position-cmd
    10  float OUT             0  hm2_7i96s.0.stepgen.04.position-fb
    10  float IN              0  hm2_7i96s.0.stepgen.04.velocity-cmd
    10  float OUT             0  hm2_7i96s.0.stepgen.04.velocity-fb
    10  bit   IN          FALSE  hm2_7i96s.0.stepgen.05.control-type
    10  s32   OUT             0  hm2_7i96s.0.stepgen.05.counts
    10  float OUT             0  hm2_7i96s.0.stepgen.05.dbg_err_at_match
    10  float OUT             0  hm2_7i96s.0.stepgen.05.dbg_ff_vel
    10  float OUT             0  hm2_7i96s.0.stepgen.05.dbg_pos_minus_prev_cmd
    10  float OUT             0  hm2_7i96s.0.stepgen.05.dbg_s_to_match
    10  s32   OUT             0  hm2_7i96s.0.stepgen.05.dbg_step_rate
    10  float OUT             0  hm2_7i96s.0.stepgen.05.dbg_vel_error
    10  bit   IN          FALSE  hm2_7i96s.0.stepgen.05.enable
    10  float IN              0  hm2_7i96s.0.stepgen.05.position-cmd
    10  float OUT             0  hm2_7i96s.0.stepgen.05.position-fb
    10  float IN              0  hm2_7i96s.0.stepgen.05.velocity-cmd
    10  float OUT             0  hm2_7i96s.0.stepgen.05.velocity-fb
    10  bit   IN          FALSE  hm2_7i96s.0.stepgen.06.control-type
    10  s32   OUT             0  hm2_7i96s.0.stepgen.06.counts
    10  float OUT             0  hm2_7i96s.0.stepgen.06.dbg_err_at_match
    10  float OUT             0  hm2_7i96s.0.stepgen.06.dbg_ff_vel
    10  float OUT             0  hm2_7i96s.0.stepgen.06.dbg_pos_minus_prev_cmd
    10  float OUT             0  hm2_7i96s.0.stepgen.06.dbg_s_to_match
    10  s32   OUT             0  hm2_7i96s.0.stepgen.06.dbg_step_rate
    10  float OUT             0  hm2_7i96s.0.stepgen.06.dbg_vel_error
    10  bit   IN          FALSE  hm2_7i96s.0.stepgen.06.enable
    10  float IN              0  hm2_7i96s.0.stepgen.06.position-cmd
    10  float OUT             0  hm2_7i96s.0.stepgen.06.position-fb
    10  float IN              0  hm2_7i96s.0.stepgen.06.velocity-cmd
    10  float OUT             0  hm2_7i96s.0.stepgen.06.velocity-fb
    10  bit   IN          FALSE  hm2_7i96s.0.stepgen.07.control-type
    10  s32   OUT             0  hm2_7i96s.0.stepgen.07.counts
    10  float OUT             0  hm2_7i96s.0.stepgen.07.dbg_err_at_match
    10  float OUT             0  hm2_7i96s.0.stepgen.07.dbg_ff_vel
    10  float OUT             0  hm2_7i96s.0.stepgen.07.dbg_pos_minus_prev_cmd
    10  float OUT             0  hm2_7i96s.0.stepgen.07.dbg_s_to_match
    10  s32   OUT             0  hm2_7i96s.0.stepgen.07.dbg_step_rate
    10  float OUT             0  hm2_7i96s.0.stepgen.07.dbg_vel_error
    10  bit   IN          FALSE  hm2_7i96s.0.stepgen.07.enable
    10  float IN              0  hm2_7i96s.0.stepgen.07.position-cmd
    10  float OUT             0  hm2_7i96s.0.stepgen.07.position-fb
    10  float IN              0  hm2_7i96s.0.stepgen.07.velocity-cmd
    10  float OUT             0  hm2_7i96s.0.stepgen.07.velocity-fb
    10  bit   IN          FALSE  hm2_7i96s.0.stepgen.08.control-type
    10  s32   OUT             0  hm2_7i96s.0.stepgen.08.counts
    10  float OUT             0  hm2_7i96s.0.stepgen.08.dbg_err_at_match
    10  float OUT             0  hm2_7i96s.0.stepgen.08.dbg_ff_vel
    10  float OUT             0  hm2_7i96s.0.stepgen.08.dbg_pos_minus_prev_cmd
    10  float OUT             0  hm2_7i96s.0.stepgen.08.dbg_s_to_match
    10  s32   OUT             0  hm2_7i96s.0.stepgen.08.dbg_step_rate
    10  float OUT             0  hm2_7i96s.0.stepgen.08.dbg_vel_error
    10  bit   IN          FALSE  hm2_7i96s.0.stepgen.08.enable
    10  float IN              0  hm2_7i96s.0.stepgen.08.position-cmd
    10  float OUT             0  hm2_7i96s.0.stepgen.08.position-fb
    10  float IN              0  hm2_7i96s.0.stepgen.08.velocity-cmd
    10  float OUT             0  hm2_7i96s.0.stepgen.08.velocity-fb
    10  bit   IN          FALSE  hm2_7i96s.0.stepgen.09.control-type
    10  s32   OUT             0  hm2_7i96s.0.stepgen.09.counts
    10  float OUT             0  hm2_7i96s.0.stepgen.09.dbg_err_at_match
    10  float OUT             0  hm2_7i96s.0.stepgen.09.dbg_ff_vel
    10  float OUT             0  hm2_7i96s.0.stepgen.09.dbg_pos_minus_prev_cmd
    10  float OUT             0  hm2_7i96s.0.stepgen.09.dbg_s_to_match
    10  s32   OUT             0  hm2_7i96s.0.stepgen.09.dbg_step_rate
    10  float OUT             0  hm2_7i96s.0.stepgen.09.dbg_vel_error
    10  bit   IN          FALSE  hm2_7i96s.0.stepgen.09.enable
    10  float IN              0  hm2_7i96s.0.stepgen.09.position-cmd
    10  float OUT             0  hm2_7i96s.0.stepgen.09.position-fb
    10  float IN              0  hm2_7i96s.0.stepgen.09.velocity-cmd
    10  float OUT             0  hm2_7i96s.0.stepgen.09.velocity-fb
    10  s32   IN             -1  hm2_7i96s.0.stepgen.timer-number
    10  bit   I/O         FALSE  hm2_7i96s.0.watchdog.has_bit
    10  s32   OUT             0  hm2_7i96s.0.write.time



 
Last edit: 17 Jun 2023 07:00 by camb0. Reason: Solved status

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16 Jun 2023 12:56 #273693 by PCW
Replied by PCW on topic How to enable/check MESA 7i96s with 7i76 daughter board - Cable/config problem??
The sserial ports on the 7I76 are channels 1 (Field I/O) and 2 (7I76 sserial expansion)
so sserial_port_0=020 (if you want mode 2 on the 7I76 field I/O section)

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16 Jun 2023 22:06 - 16 Jun 2023 22:07 #273720 by camb0
Replied by camb0 on topic How to enable/check MESA 7i96s with 7i76 daughter board - Cable/config problem??
Thx for the explanation of the sserial_port it's really useful, however I probably should have phrased the question better.  I can't see the 7i76, hence I was looking at the sserial_port setting as something that might be preventing me from seeing it.

My intent is to use the 7i76 for additional IO as I don't have enough ports on the 7i96 for limit switches + tool changer + other items.  From the manual and your message it looks like I should be setting it up for mode 1 (all IO plus the analog ports). So that would be a config string of:
halcmd: loadrt hm2_eth board_ip="10.10.10.10" config="sserial_port_0=010"

This issue I have is that when I do that I only see 51 pins which I'm pretty sure is just the 7i96s as per below.  Any other hints as to what mistake/omission/tests I can do to verify I've got it setup correctly?
halcmd: loadrt hm2_eth board_ip="10.10.10.10" config="sserial_port_0=010"
hm2_eth: loading Mesa AnyIO HostMot2 ethernet driver version 0.2
hm2_eth: 10.10.10.10: INFO: Hardware address (MAC): 00:60:1b:16:86:5e
hm2_eth: discovered 7I96S
hm2/hm2_7i96s.0: Low Level init 0.15
hm2/hm2_7i96s.0: Smart Serial Firmware Version 43
hm2/hm2_7i96s.0: 51 I/O Pins used:
hm2/hm2_7i96s.0:     IO Pin 000 (TB3-01): InM Input Module #0, pin in0 (Input).....
Last edit: 16 Jun 2023 22:07 by camb0. Reason: formatting

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16 Jun 2023 22:52 #273722 by PCW
Replied by PCW on topic How to enable/check MESA 7i96s with 7i76 daughter board - Cable/config problem??
The reason I mentioned the sserial_port_0 is that your original example would have disabled the 7I76.

The 7I76 is still not being detected

So it may be cabling or power

So you have both 5V and field power?

7I76 W1 and W3 Left?

Here is what I get running a 7I96S+7I76 with 7i96s_7i76d.bin firmware:

 

File Attachment:

File Name: 7i96s_7i76.txt
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16 Jun 2023 23:20 #273724 by camb0
Replied by camb0 on topic How to enable/check MESA 7i96s with 7i76 daughter board - Cable/config problem??
Thx, I’m suspicious of the cable.

I’ve tested it with power to the board and power via the db25 cable (swapping the jumpers to suit), both times the LED’s were on and green.
I’ll double check the jumpers when I get home.
I’ve got power to the field (24v).

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17 Jun 2023 00:37 #273728 by camb0
Replied by camb0 on topic How to enable/check MESA 7i96s with 7i76 daughter board - Cable/config problem??
With logic power coming via the DB25 (5v) and field power via TB1 (24v) I've got:
W1 = right (VIN SEP)
W2 = left (5v FPGA)
W3 = left

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17 Jun 2023 01:00 #273729 by camb0
Replied by camb0 on topic How to enable/check MESA 7i96s with 7i76 daughter board - Cable/config problem??
I've bench tested the continuity of the pins with my volt meter, they're all connected. 
I've checked pin 1 against the diagrams and I think I've got it correct but I might have misread it.
Here's a pic of the cable with pin 1's aligned (note the 26pin end has a socket on it to make it easier to test) the 26 pin locating boss is on the left (first pic).
Last pic is of the cable installed.
 
 
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17 Jun 2023 02:47 #273730 by PCW
Replied by PCW on topic How to enable/check MESA 7i96s with 7i76 daughter board - Cable/config problem??
W1 must be in the left position
The following user(s) said Thank You: camb0

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17 Jun 2023 05:15 #273733 by camb0
Replied by camb0 on topic How to enable/check MESA 7i96s with 7i76 daughter board - Cable/config problem??
Yahtzee!!!!
I see the 7i76 now, thx a bunch for your assistance and patience.
The following user(s) said Thank You: tommylight

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