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I sent the header board schematic fileSo are you saying that the FPGA board has undefined states at its I/O pinsif they are floated so require the interfacing hardware to have pullupsor pulldowns to define the state after a watchdog bite?That might explain the issue if the interfacing hardware lacks these.
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Hello
No it doesn't, neither ghosted. Works great (200+hrs so far, many parts). The I/O states are initialized and maintained hardware-wise (pullups/pulldowns). That's the machine-tool builder's responsability when designing the interfacing board/pcb.
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