Transformer isolation outputs

While looking at options to add a few isolated outputs to my 7i92th. I recalled a post by PCW " here " saying the SSR module is for transformer isolation. Sounds interesting.

After reading the hostmot2 SSR section of the docs and taking a close look at my 7i96s as a reference. I think I have a grasp on how this is being done. However I do have a few questions.

 I assume the line driver / buffer protects the fpga pins and can better drive the primary coil. Is a inverted output line driver / buffer required or would a non inverted IC work the same? 

 How critical is capacitor value? I was unsure how to properly calculate the values for the primary and secondary transformer capacitors.

Here is what I came up with for adding a few SSR outputs to my 7i92th (heavily 7i96s influenced). I wanted to get some feedback before routing the board traces and ordering a pcb. Some components differ from what is on my 7i96s, I am just trying to use what I have on hand. I can however make changes if I have made poor component selections.



Thank you in advance for your advice.

That looks right except the capacitor values (we use 0.1 uF for the non isolated side and 1000 pF for the isolated side)

inverted or non-inverted work the same

Not really safe to drive the xfrmer with the direct FPGA outputs (plus it would only be 3.3V vs 5V)

tommylight wrote:

You should wait for PCW to confirm this, but i am pretty sure transformers can not be used for DC signaling.

That was my first thought as well. Then after reading the ssr section of the docs I realized it was using pwm. Reminds me of a half bridge transformer coupled gate drive circuit. With only the one mosfet as our output instead of flip flopping two.

PCW wrote:

That looks right except the capacitor values (we use 0.1 uF for the non isolated side and 1000 pF for the isolated side)

inverted or non-inverted work the same

Not really safe to drive the xfrmer with the direct FPGA outputs (plus it would only be 3.3V vs 5V)

Thank you for the schematic review and value recommendations. That makes sense, I don't know why I forgot about the fpga being 3.3v. I need to be more mindful of that.

On the hostmot2 side of things does this act like a single ended gate drive with just the one pwm signal. Or more like a double ended setup with two opposite polarity pwm signals?

Basically just two square waves, the reference
and the outputs. When off the outputs are in phase
with the reference, when on, the outputs are 180
degrees relative to the reference.

@PCW Thanks for confirming. That is how I understood the ssr man page but was not 100% sure.


This is what I have at this point. A simple daughter (little-sister ? lol) board. Measuring roughly 50x50 with direct din mounting, pluggable terminal blocks and idc header. The DSS-SSR4 gives me x4 additional isolated SSR outputs. I really like the 7i92+g540 combo for simple systems. However I often need just a few more outputs then the two onboard the g540 and not all systems warrant a full daughter card.



After I have a chance to assemble / test the board, I will be putting all of the documentations and source files on my GitHub acct.

One of these days I will finish my re-flow oven. Soldering would have gone much faster and come out cleaner if I was not doing it by hand. Test board assembled and ready to hook up to my Mesa 7i92th. I am not sure how I missed it, but you can see the idc hdr needs to be rotated 180*. This has no functional benefit but will ease ribbon cable routing in my electrical cabinet (no twist in ribbon).

And one custom Bin file later. It's Alive ! haha I will need to fix a few simple errors such as silkscreen, hdr orientation ect. Otherwise we have transformer isolated outputs; how cool .

Video does not want to embed properly; lets try a link. " Video "

In regards to the Bin file: @PCW after synthesizing in Efinity, within the Result tab under Interface. I get a "Unassigned Core Pins: 2" error. Otherwise no problems and the file flashes and functions exactly as expected. I am new to the Efinity IDE and was unsure if that was a result of my new pin vhd work.

The unassigned core pins are probably TP0 and TP1,
leftovers from performance testing. I haven't bothered
to remove them yet, the message is harmless.

I have the board about where I want it for my use case. I will be organizing my files and posting to GitHub shortly.