RV901T as MESA 7i90: Custom bitstream generation with PWMTag leads to error

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2 years 7 months ago - 2 years 7 months ago #297342 by ago_tm
Hello guys,

I am failing to see how this is a LinuxCNC question or issue ?!?!
Probably should be in "computers and hardware as it is for RPI ...

I am very sorry, you are right - my questions are more about the hardware for linuxcnc, but not the linuxcnc itself.
I will appreciate if you could help me to move this thread to the corresponding topic (if it is possible).

From my side I promise to be more accurate in future.
Last edit: 2 years 7 months ago by ago_tm.

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2 years 7 months ago #297360 by tommylight
Moving stuff is easy, so no need to be sorry at all.
Double posting the same subject makes a mess for whoever is trying to help.
I will move this later, as i am on the phone.
Thank you.

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2 years 7 months ago #297364 by tommylight
The following user(s) said Thank You: ago_tm

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2 years 6 months ago - 2 years 6 months ago #297530 by ago_tm
Hello guys,

I still trying the find a possible solution for my issue.
I do not have hard skills in fpga but I am trying to dig it deeper and will appreciate if you could help me with understanding when there is a mistake in my conclusions.

As I said before enabling of at least the only PWM out leads to error I will focus on the single pin PWMAOutPin
Code:
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 0 PWM OUT

According to the error message and your help I see that the problem is in different sites used for PWM module clocking and the component "SP6_BUFIO_INSERT_ML_BUFIO2_1".

First problem is that I do not understand what the component it is... It looks like some kind of implicitly named component of the design. I just assume that it is something related to the PWM module.

In TopGCSPIHostMot2.vhd line 306 I found the confirmation that the PWM clock frequency should be 200 MHz:
Code:
clkhigh => fclk, -- PWM clock

fclk is the output of the BUFG_inst0 where the input is clkfx0, which is CLKFX endpoint of ClockMultH digital clock manager, which is
Code:
Oscillator's CLK (25) MHz * CLKFX_MULTIPLY (16) / CLKFX_DIVIDE (2) = 200 MHz

So it looks like the truth: PWM module depends on the CLK which is package pin M9 and in PlanAhead I see for it:
Code:
Instance: CLK_IBUFG Net: CLK Package pin: M9 Site type: IO_L29P_GCLK3_2 Bank: I/O Bank: 2 (Standard) Tile: BIOB_X12Y0 Clock region: X1Y0

As I also see: clock region X1Y0 is the bottom right part of the crystal.

In UG382 I found that BUFIO2_X4Y21 is related to Bank 1:
Code:
GCLK_10 <BUFIO2_X4Y21> GCLK_6 <BUFIO2_X4Y21>

I understand that I need to somehow create a LOC constraint.
In the Constraints Guide I found the following example:
Code:
INST “instance_name ” LOC=location;

But I do not know what it means "SP6_BUFIO_INSERT_ML_BUFIO2_1"? I can't find anything with that name in PlanAhead. If it is a primitive, how can I find it?
What location should be in my case - some free BIOB_ from clock region X1Y0, for example BIOB_SINGLE_X13Y0 or BIOB_X15Y0?

I will appreciate the further help.
Last edit: 2 years 6 months ago by ago_tm.

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2 years 6 months ago - 2 years 6 months ago #297536 by PCW
Still sounds like a clock setup error of some kind
maybe an introduced error in the DCM/BUFG setup
in the source.

 The SPI clock is picky because it directly drives a GCLK
that runs SPI interface logic.

The multiplied clocks are available globally  on a global clock spine
so the PWM  pinout does not matter at all.


Can you post your .ucf file?

It may be that you have a conflict between the SPI GCLK and the DCM source

Taking a look at ug382.pdf might help
Last edit: 2 years 6 months ago by PCW.

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2 years 6 months ago #297547 by ago_tm
Hello Peter,

Can you post your .ucf file?
Sure, here it is:
github.com/golyakoff/hostmot2-rv901t-7i9...b/master/7i90spi.ucf
(this is the complete repo of original hostmot2 with separately commited my overrides).

It may be that you have a conflict between the SPI GCLK and the DCM source

Taking a look at ug382.pdf might helpc
I started reading the manuals but not all is clear for me yet...

Did I understand the key concept right?

There are two different time domains:
1. CLK (M9) 25 MHz from the own board oscillator
2. COM_SPICLK (P59) External from RPI (24 MHz if I coerrectly remember)

...and the RPI send commands over SPI for PWM, wh8ch is driving by CLK (as you say GCLK, but I do not understand the difference). And these time domains are not synchronized and they shouldn't be... right?

Is this right?

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