7i95 + serial absolute encoder

Thank you, do you have any example config / docs / link how to use it with hostmot2 where I can begin?
Thank you
Tamas

You can look at the SSI section of the hostmot2 manual page
man hostmot2

Also I think tommylight has some example SSI configurations

So I have configured it, but it doesn't work properly:
relevant HAL section:

loadrt hm2_eth board_ip="192.168.1.121" config="num_stepgens=5 num_encoders=5 ssi_chan_0=position%25ge"

#SSI stuff
#setp hm2_7i95.0.dpll.base-freq-khz 1.007
setp hm2_7i95.0.ssi.00.frequency-khz 800
#setp hm2_7i95.0.ssi.00.timer-number 1
setp hm2_7i95.0.dpll.01.timer-us -100

Encoder is Leine & Linde ISA 608, output is 25 bit gray.

I always get "data transmission not complete ..." error, regardless of clock frequency/ timer / dpll base freq values.
Theoretically this encoder supports up to 1Mhz clock freq.

position.counts is always 23773199 or close to.
I checked polarity of clock/data signals, also have seen clock signal with oscilloscope.

For sure, my 7i95 card has some hardware issues what I already asked it here, but due to chip issue and long time of post (from EU to US and return) I didn't want to request RMA.
Here is the mentioned topic: forum.linuxcnc.org/27-driver-boards/37894-mesa-7i95?start=230

Can we rule out that this issue might impact the communication on the SSI interface?

Plan B: I have an unused 7i96s, could you PCW please make me a bitfile with SSI support? To test if this issue is related to 7i95.

Any other clue please?

Thank you
Tamas

#setp hm2_7i95.0.dpll.base-freq-khz 1.007
setp hm2_7i95.0.ssi.00.frequency-khz 800
#setp hm2_7i95.0.ssi.00.timer-number 1
setp hm2_7i95.0.dpll.01.timer-us -100

Without the timer specified you are guaranteed to get
a data transmission not complete error.

Also you should never have to change the DPLL base frequency
since it's set to the servo thread frequency as the default.

If not a clock or data polarity issue, my guess is that you do not have
DPLL lock for some reason. I would check this by either watching
or halscope plotting hm2_7i95.0.dpll.phase-error-us

Here is an normal plot of the DPLL error (at 100 usec per division) when locked:

 

Here is a plot (also 100 usec per division) where DPLL lock has been lost:

 
 

7I96S config with SSI replacing the sserial port:

 
 

Thanks a lot, encoder works. Encoder had wrong configuration because output signal level was TTL instead of RS422.
Also works with my 7i95.