Xilinx Zynq 7010 fpga crypto windfall boards

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1 year 4 months ago #330394 by meister
so I can at least create a bitfile for flashing LEDs, but I don't know if it works:

bin/rio-generator -b riocore/configs/XC7Z010/config.json
Code:
loading: riocore/configs/XC7Z010/config.json loading board setup: XC7Z010 loading toolchain vivado writing gateware to: Output/XC7Z010/Gateware !!! gateware changed: needs to flash ||| writing linuxcnc files to: Output/XC7Z010/LinuxCNC running:   (cd Output/XC7Z010/Gateware && make clean all) rm -rf build rio.tcl *.jou *.log .Xil vivado -mode batch -source rio.tcl ****** Vivado v2023.1 (64-bit)   **** SW Build 3865809 on Sun May  7 15:04:56 MDT 2023   **** IP Build 3864474 on Sun May  7 20:36:21 MDT 2023   **** SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023     ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.     ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. .... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./build/rio.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-83] Releasing license: Implementation 9 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:05 ; elapsed = 00:00:14 . Memory (MB): peak = 2987.496 ; gain = 232.207 ; free physical = 2245 ; free virtual = 14339 # exit INFO: [Common 17-206] Exiting Vivado at Tue Jun 17 14:27:34 2025... cp -v hash_new.txt hash_compiled.txt 'hash_new.txt' -> 'hash_compiled.txt'
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1 year 4 months ago #330396 by unknown
So does that I'll have to buy one to play with the cool kids ?

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1 year 4 months ago #330397 by meister
;P
the part is very tricky, at the moment i can't tell if it works and the ARM cores on it want extra love but i don't know how to configure them.
Ethernet won't work for now either, so if it does then only SPI and maybe later a bridge via the ARM cores.

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1 year 4 months ago #330427 by DMNZ
I have ordered one from aliexpress for evil experiments, but i am total newbie in fpga so a single AND gate with two buttons and blinking led is all I can dream about so far. image missing /media/kunena/emoticons/smile.png
i can see you use 2023.1 version of vivado, do you find it better over the newer ones? 

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1 year 4 months ago #330432 by meister
so far there has been no reason for an update,
but i also don't use the IDE but only the console tools

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1 year 4 months ago #330613 by timo
Just a comment from enduser perspective.

( I already struggle hard to get my small wiring project organized. "cable management" :-) )
Diving into "building Linux from source", and fighting drivers etc. seems to be completely unreal.
Most (or only some?) people already having a hard time with the hal configuration and getting basic UI functions to work.

How many thousand hours do I have to spend extra in sofware research and learning new things, in order to save 60 coins on a control card?

Considering the cost of mechanical components (e.g. for metal working machines), the FPGA card is the least financial problem.

I feel that leaves a very small target group beeing interested in a "race to the bottom" with FPGA card pricing. This target group is also looking into 3d printer firmware and hardware. (cheap, and for some things usable)

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