1. Hardware & Machines
  3. Driver Boards
  5. Bitfile for Mesa 7i96s + 7i85 (+Modbus (PKT-Pin))

Bitfile for Mesa 7i96s + 7i85 (+Modbus (PKT-Pin))

More
09 Dec 2025 08:44 #339902 by TripleM
Bitfile for Mesa 7i96s + 7i85 (+Modbus (PKT-Pin)) was created by TripleM
Hello,

My current configuration consists of a 7i96s and a 7i85. A 7i84 is connected to the 7i96s via Smart Serial.
By default, I can flash the original bit file "PIN_7I96S_7I85D_51".

Now I would like to add a PktUART pin for Modbus. Is it possible to connect Modbus to the 7i85, or is that only possible directly with the 7i96s?
My suggestion is attached, but unfortunately, I'm not sure if it's correct.

I've added the following to the first block:
        (PktUARTTTag,            x"02",    ClockLowTag,        x"01",    PktUARTTDataAddr&PadT,            PktUARTTNumRegs,        x"00",    PktUARTTMPBitMask),      
        (PktUARTRTag,            x"02",    ClockLowTag,        x"01",    PktUARTRDataAddr&PadT,            PktUARTRNumRegs,        x"00",    PktUARTRMPBitMask),

If I link the pins to the 7i85, does that mean I'll use two Smart Serial pins?
Attachments:

Please Log in or Create an account to join the conversation.

  • tommylight
  • tommylight's Avatar
  • Away
  • Moderator
  • Moderator
More
19 Dec 2025 00:26 - 19 Dec 2025 18:35 #340292 by tommylight
Replied by tommylight on topic Bitfile for Mesa 7i96s + 7i85 (+Modbus (PKT-Pin))
What if you connect the 7i84 to the 7i85 and use the 7i96S SSerial for PktUART ?
Just an idea as wiring the 7i84 to 7i85 works without any setup and requires simple unplug from 7i96S and plug to 7i85, but also editing the hal to change the SSerial card channel.
Edit:
See below about SSerial on 7i96S and 7i85
Last edit: 19 Dec 2025 18:35 by tommylight. Reason: more info

Please Log in or Create an account to join the conversation.

More
19 Dec 2025 01:18 #340294 by PCW
Replied by PCW on topic Bitfile for Mesa 7i96s + 7i85 (+Modbus (PKT-Pin))
tommylights suggestion is on the right track,
Modbus needs RS-485 and the 7I85 serial interfaces
are RS-422 only (no TXEN).
The following user(s) said Thank You: tommylight

Please Log in or Create an account to join the conversation.

  • tommylight
  • tommylight's Avatar
  • Away
  • Moderator
  • Moderator
More
19 Dec 2025 02:35 #340296 by tommylight
Replied by tommylight on topic Bitfile for Mesa 7i96s + 7i85 (+Modbus (PKT-Pin))
Is the "unplug and plug" thing correct, meaning is it the same pinout for SSerial on 7i96S and 7i85?
Sorry if i messed that up, i never used a 7i85, yet, it was just an educated guess from experience with Mesa boards and very consistent pinout.

Please Log in or Create an account to join the conversation.

More
19 Dec 2025 18:13 #340309 by PCW
Replied by PCW on topic Bitfile for Mesa 7i96s + 7i85 (+Modbus (PKT-Pin))
Yes, the sserial pinouts on the 7I85 and 7I96S are similar except the 7I85 uses 8 pins and the 7I96S uses 6
You can plug a 6 pin sserial connector into the 7I85 if you center it, that is with  a 1 pin gap in each side.
The 8 pin connection uses duplicated power and ground pins. On the 6 pin connector, you must terminate
2 wires in the single power and ground pins.
 
The following user(s) said Thank You: tommylight

Please Log in or Create an account to join the conversation.

More
23 Dec 2025 08:40 - 23 Dec 2025 08:46 #340414 by TripleM
Replied by TripleM on topic Bitfile for Mesa 7i96s + 7i85 (+Modbus (PKT-Pin))
ok, I will put the 7i85 on the Serialport from 7i84 and I modify the 7I96S_7I85D_51 Bitfile.
If I plug it in serial_0 i don´t have to change the hal-file?! 
sserial_port_0=2xxxxxxx

The bit file workflow was completed without errors, and the bit file was created. Can anything go wrong during flashing, other than it not working?
library IEEE;
use IEEE.std_logic_1164.all;  -- defines std_logic types
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
--    * GNU General Public License (GPL), version 2.0 or later
--    * 3-clause BSD License
-- 
--
-- The GNU GPL License:
-- 
--     This program is free software; you can redistribute it and/or modify
--     it under the terms of the GNU General Public License as published by
--     the Free Software Foundation; either version 2 of the License, or
--     (at your option) any later version.
-- 
--     This program is distributed in the hope that it will be useful,
--     but WITHOUT ANY WARRANTY; without even the implied warranty of
--     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--     GNU General Public License for more details.
-- 
--     You should have received a copy of the GNU General Public License
--     along with this program; if not, write to the Free Software
--     Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-- 
-- 
-- The 3-clause BSD License:
-- 
--     Redistribution and use in source and binary forms, with or without
--     modification, are permitted provided that the following conditions
--     are met:
-- 
--   * Redistributions of source code must retain the above copyright
--     notice, this list of conditions and the following disclaimer.
-- 
--   * Redistributions in binary form must reproduce the above
--     copyright notice, this list of conditions and the following
--     disclaimer in the documentation and/or other materials
--     provided with the distribution.
-- 
--   * Neither the name of Mesa Electronics nor the names of its
--     contributors may be used to endorse or promote products
--     derived from this software without specific prior written
--     permission.
-- 
-- 
-- Disclaimer:
-- 
--     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
--     "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
--     LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
--     FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
--     COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
--     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
--     BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
--     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
--     CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--     LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
--     ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--     POSSIBILITY OF SUCH DAMAGE.
-- 

use work.IDROMConst.all;

package PIN_7I96S_7I85D_51_pkt is
	constant ModuleID : ModuleIDType :=( 
		(HM2DPLLTag,	x"00",	ClockLowTag,	x"01",	HM2DPLLBaseRateAddr&PadT,	HM2DPLLNumRegs,		x"00",	HM2DPLLMPBitMask),
		(WatchDogTag,	x"00",	ClockLowTag,	x"01",	WatchDogTimeAddr&PadT,		WatchDogNumRegs,		x"00",	WatchDogMPBitMask),
		(IOPortTag,		x"00",	ClockLowTag,	x"03",	PortAddr&PadT,					IOPortNumRegs,			x"00",	IOPortMPBitMask),
		(OutMTag,				x"00",	ClockLowTag,	x"01",	OutMDataAddr&PadT,		   OutMNumRegs,			x"00",	OutMMPBitMask),
		(PWMTag,			x"00",	ClockHighTag,	x"01",	PWMValAddr&PadT,				PWMNumRegs,				x"00",	PWMMPBitMask),
		(StepGenTag,	x"02",	ClockLowTag,	x"05",	StepGenRateAddr&PadT,		StepGenNumRegs,		x"00",	StepGenMPBitMask),
		(MuxedQcountTag,		MQCRev,	ClockLowTag,	x"06",	MuxedQcounterAddr&PadT,		MuxedQCounterNumRegs,x"00",	MuxedQCounterMPBitMask),
		(MuxedQCountSelTag,	x"00",	ClockLowTag,	x"01",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(SSerialTag,	x"00",	ClockLowTag,	x"01",	SSerialCommandAddr&PadT,	SSerialNumRegs,		x"10",	SSerialMPBitMask),
		(XFrmrOutTag,	x"00",	ClockLowTag,	x"01",	XFrmrDataAddr&PadT,			XFrmrNumRegs,			x"00",	XFrmrMPBitMask ),
		(InMTag,					x"00",	ClockLowTag,	x"01",	InMControlAddr&PadT,			InMNumRegs,				x"00",	InMMPBitMask),
		(LEDTag,			x"00",	ClockLowTag,	x"01",	LEDAddr&PadT,					LEDNumRegs,				x"00",	LEDMPBitMask),
		--(NullTag,				x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		--(NullTag,				x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(PktUARTTTag,			x"02",	ClockLowTag,	    x"01",	PktUARTTDataAddr&PadT,		    PktUARTTNumRegs,		x"00",	PktUARTTMPBitMask),  	--+++add
		(PktUARTRTag,			x"02",	ClockLowTag,	    x"01",	PktUARTRDataAddr&PadT,		    PktUARTRNumRegs,		x"00",	PktUARTRMPBitMask),		--+++add
		(NullTag,				x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,				x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,				x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,				x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,				x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,				x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,				x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,				x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,				x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,				x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,				x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,				x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,				x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,				x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,				x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,				x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,				x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(InMWidth0Tag,			x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"0000000B") -- hide this tag here until we find a better way
		);
			
	constant PinDesc : PinDescType :=(
	
-- 	Base func  sec unit sec func 	sec pin						 	      
		
																						--		
		IOPortTag & x"00" & InMTag & InMData0Pin,     			  		-- I/O 00 	embedded 7I96 Simple I/O
		IOPortTag & x"00" & InMTag & InMData1Pin,   			  		-- I/O 01   	
		IOPortTag & x"00" & InMTag & InMData2Pin,   			  		-- I/O 02   
		IOPortTag & x"00" & InMTag & InMData3Pin,  			  	   	    -- I/O 03		
		IOPortTag & x"00" & InMTag & InMData4Pin,   			   	 	-- I/O 04	
		IOPortTag & x"00" & InMTag & InMData5Pin,  			      	    -- I/O 05		
		IOPortTag & x"00" & InMTag & InMData6Pin,  			     		-- I/O 06   
		IOPortTag & x"00" & InMTag & InMData7Pin,       				-- I/O 07   	
		IOPortTag & x"00" & InMTag & InMData8Pin,    					-- I/O 08   
		IOPortTag & x"00" & InMTag & InMData9Pin,       				-- I/O 09   
		IOPortTag & x"00" & InMTag & InMDataAPin,       				-- I/O 10   
		IOPortTag & x"00" & XfrmrOutTag & XfrmrOut0Pin, 			  	-- I/O 11   
		IOPortTag & x"00" & XfrmrOutTag & XfrmrOut1Pin,  			 	-- I/O 12   
		IOPortTag & x"00" & XfrmrOutTag & XfrmrOut2Pin,  			 	-- I/O 13		
		IOPortTag & x"00" & XfrmrOutTag & XfrmrOut3Pin,  			 	-- I/O 14   	
		IOPortTag & x"00" & OutMTag & OutMData4Pin,   		            -- I/O 15   	
		IOPortTag & x"00" & OutMTag & OutMData5Pin,   		            -- I/O 16   	

		IOPortTag & x"00" & StepGenTag & StepGenStepPin,				-- I/O 17	embedded 7I96 Step/Dir/Enc/Serial
		IOPortTag & x"00" & StepGenTag & StepGenDirPin,					-- I/O 18	
		IOPortTag & x"01" & StepGenTag & StepGenStepPin,				-- I/O 19	
		IOPortTag & x"01" & StepGenTag & StepGenDirPin,					-- I/O 20	
		IOPortTag & x"02" & StepGenTag & StepGenStepPin,				-- I/O 21	
		IOPortTag & x"02" & StepGenTag & StepGenDirPin,					-- I/O 22	
		IOPortTag & x"03" & StepGenTag & StepGenStepPin,				-- I/O 23	
		IOPortTag & x"03" & StepGenTag & StepGenDirPin,					-- I/O 24	
		IOPortTag & x"04" & StepGenTag & StepGenStepPin,				-- I/O 25	
		IOPortTag & x"04" & StepGenTag & StepGenDirPin,					-- I/O 26	
		IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQAPin,		    -- I/O 27
		IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQBPin,		    -- I/O 28	
		IOPortTag & x"02" & MuxedQCountTag & MuxedQCountIDXPin,		    -- I/O 29	
		IOPortTag & x"00" & PktUARTRTag & PktURDataPin, 				-- I/O 30   +++add
		IOPortTag & x"00" & PktUARTTTag & PktUTDataPin,  				-- I/O 31   +++add
		IOPortTag & x"00" & PktUARTTTag & PktUTDrvEnPin,				-- I/O 32   +++add
		IOPortTag & x"00" & XfrmrOutTag & XfrmrRefPin,    				-- I/O 33
		
																		--		Expansion port
																		-- GPIO     DB25		HDR26
		IOPortTag & x"00" & SSerialTag & SSerialRX5Pin, 				-- I/O 34	PIN 1    PIN 1	 	
		IOPortTag & x"00" & SSerialTag & SSerialTX5Pin, 				-- I/O 35	PIN 14   PIN 2		
		IOPortTag & x"00" & SSerialTag & SSerialRX4Pin, 				-- I/O 36	PIN 2    PIN 3		
		IOPortTag & x"00" & SSerialTag & SSerialTX4Pin, 				-- I/O 37	PIN 15   PIN 4	
		IOPortTag & x"00" & SSerialTag & SSerialRX3Pin, 				-- I/O 38	PIN 3    PIN 5	
		IOPortTag & x"00" & SSerialTag & SSerialTX3Pin, 				-- I/O 39	PIN 16   PIN 6	
		IOPortTag & x"00" & SSerialTag & SSerialRX2Pin, 				-- I/O 40	PIN 4    PIN 7	
		IOPortTag & x"00" & SSerialTag & SSerialTX2Pin, 				-- I/O 41	PIN 17   PIN 8	
		IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, 				-- I/O 42	PIN 5    PIN 9	
		IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, 				-- I/O 43	PIN 6    PIN 11
		IOPortTag & x"00" & MuxedQCountSelTag & MuxedQCountSel0Pin, 	-- I/O 44	PIN 7    PIN 13
		IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQAPin,		    -- I/O 45	PIN 8    PIN 15
		IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQBPin,		    -- I/O 46	PIN 9    PIN 17
		IOPortTag & x"00" & MuxedQCountTag & MuxedQCountIDXPin,		    -- I/O 47	PIN 10   PIN 19
		IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQAPin,		    -- I/O 48	PIN 11   PIN 21
		IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQBPin,		    -- I/O 49	PIN 12   PIN 23
		IOPortTag & x"01" & MuxedQCountTag & MuxedQCountIDXPin,		    -- I/O 50	PIN 13   PIN 25

		LIOPortTag & x"00" & PWMTag  & PWMAOutPin, 						-- 7I96S analog out PWM
		LIOPortTag & x"00" & PWMTag  & PWMBDirPin, 						-- dummy for now
																										
		emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, 
		emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,

		emptypin,emptypin,emptypin,emptypin,emptypin,
		emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
		emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
		
		emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
		emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
		emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
		emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
		emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
		emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
		emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);

end package PIN_7I96S_7I85D_51_pkt;
Last edit: 23 Dec 2025 08:46 by TripleM.

Please Log in or Create an account to join the conversation.

More
23 Dec 2025 16:17 #340425 by PCW
Replied by PCW on topic Bitfile for Mesa 7i96s + 7i85 (+Modbus (PKT-Pin))
I would probably renumber the sserial channels so the 7I85 sserial channels start at 0 rather than 1

Flashing is safe as long as you have a recent mesaflash that supports the 7I96S

Please Log in or Create an account to join the conversation.

More
28 Dec 2025 09:31 #340617 by TripleM
Replied by TripleM on topic Bitfile for Mesa 7i96s + 7i85 (+Modbus (PKT-Pin))
I tested the bit file...
The good news: nothing is damaged. But I got this error
Debug file information:
Note: Using POSIX realtime
hm2/hm2_7i96s.0: Unsupported or inconsistent PktUART TX module (version 3)not loading driver 
hm2/hm2_7i96s.0: failed to parse Module Descriptor 12
hm2_eth: rtapi_app_main: Invalid argument (-22)

Should I use version 2?
I change the Version by editing x"03"--> x"02"?:
(PktUARTTTag,        x"03",    ClockLowTag,            x"01",    PktUARTTDataAddr&PadT,        PktUARTTNumRegs,         x"00",    PktUARTTMPBitMask),
        (PktUARTRTag,        x"03",    ClockLowTag,            x"01",    PktUARTRDataAddr&PadT,        PktUARTRNumRegs,        x"00",    PktUARTRMPBitMask),

Configuration Name: HOSTMOT2

General configuration information:

  BoardName : MESA7I96
  FPGA Size: 20 KGates
  FPGA Pins: 256
  Number of IO Ports: 3
  Width of one I/O port: 17
  Clock Low frequency: 100.0000 MHz
  Clock High frequency: 160.0000 MHz
  IDROM Type: 3
  Instance Stride 0: 4
  Instance Stride 1: 64
  Register Stride 0: 256
  Register Stride 1: 256

Modules in configuration:

  Module: DPLL
  There are 1 of DPLL in configuration
  Version: 0
  Registers: 7
  BaseAddress: 7000
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: WatchDog
  There are 1 of WatchDog in configuration
  Version: 0
  Registers: 3
  BaseAddress: 0C00
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: IOPort
  There are 3 of IOPort in configuration
  Version: 0
  Registers: 5
  BaseAddress: 1000
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: OutM
  There are 1 of OutM in configuration
  Version: 0
  Registers: 1
  BaseAddress: B000
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: PWM
  There are 1 of PWM in configuration
  Version: 0
  Registers: 5
  BaseAddress: 4100
  ClockFrequency: 160.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: StepGen
  There are 5 of StepGen in configuration
  Version: 2
  Registers: 10
  BaseAddress: 2000
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: MuxedQCount
  There are 6 of MuxedQCount in configuration
  Version: 4
  Registers: 5
  BaseAddress: 3600
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: MuxedQCountSel
  There are 1 of MuxedQCountSel in configuration
  Version: 0
  Registers: 0
  BaseAddress: 0000
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: SSerial
  There are 1 of SSerial in configuration
  Version: 0
  Registers: 6
  BaseAddress: 5B00
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 64 bytes

  Module: SSR
  There are 1 of SSR in configuration
  Version: 0
  Registers: 2
  BaseAddress: 7D00
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: InM
  There are 1 of InM in configuration
  Version: 0
  Registers: 5
  BaseAddress: 8500
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: LED
  There are 1 of LED in configuration
  Version: 0
  Registers: 1
  BaseAddress: 0200
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: PktUARTTX
  There are 1 of PktUARTTX in configuration
  Version: 3
  Registers: 4
  BaseAddress: 6100
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: PktUARTRX
  There are 1 of PktUARTRX in configuration
  Version: 3
  Registers: 4
  BaseAddress: 6500
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

Configuration pin-out:

IO Connections for TB3 -> 7I96_0
Pin#                  I/O   Pri. func    Sec. func        Chan     Sec. Pin func   Sec. Pin Dir

TB3-1                   0   IOPort       InM              0        Input0_EncA0    (In)
TB3-2                   1   IOPort       InM              0        Input1_EncB0    (In)
TB3-3                   2   IOPort       InM              0        Input2_EncA1    (In)
TB3-4                   3   IOPort       InM              0        Input3_EncB1    (In)
TB3-5                   4   IOPort       InM              0        Input4_EncA2    (In)
TB3-6                   5   IOPort       InM              0        Input5_EncB2    (In)
TB3-7                   6   IOPort       InM              0        Input6_EncA3    (In)
TB3-8                   7   IOPort       InM              0        Input7_EncB3    (In)
TB3-9                   8   IOPort       InM              0        Input8          (In)
TB3-10                  9   IOPort       InM              0        Input9          (In)
TB3-11                 10   IOPort       InM              0        Input10         (In)
TB3-13,14              11   IOPort       SSR              0        Out-00          (Out)
TB3-15,16              12   IOPort       SSR              0        Out-01          (Out)
TB3-17,18              13   IOPort       SSR              0        Out-02          (Out)
TB3-19,20              14   IOPort       SSR              0        Out-03          (Out)
TB3-21,22              15   IOPort       OutM             0        Output4         (Out)
TB3-23,24              16   IOPort       OutM             0        Output5         (Out)

IO Connections for TB1/TB2 -> 7I96_1
Pin#                  I/O   Pri. func    Sec. func        Chan     Sec. Pin func   Sec. Pin Dir

TB1-2,3                17   IOPort       StepGen          0        Step/Table1     (Out)
TB1-4,5                18   IOPort       StepGen          0        Dir/Table2      (Out)
TB1-8,9                19   IOPort       StepGen          1        Step/Table1     (Out)
TB1-10,11              20   IOPort       StepGen          1        Dir/Table2      (Out)
TB1-14,15              21   IOPort       StepGen          2        Step/Table1     (Out)
TB1-16,17              22   IOPort       StepGen          2        Dir/Table2      (Out)
TB1-20,21              23   IOPort       StepGen          3        Step/Table1     (Out)
TB1-22,23              24   IOPort       StepGen          3        Dir/Table2      (Out)
TB2-2,3                25   IOPort       StepGen          4        Step/Table1     (Out)
TB2-4,5                26   IOPort       StepGen          4        Dir/Table2      (Out)
TB2-7,8                27   IOPort       MuxedQCount      2        MuxQ-A          (In)
TB2-10,11              28   IOPort       MuxedQCount      2        MuxQ-B          (In)
TB2-13,14              29   IOPort       MuxedQCount      2        MuxQ-IDX        (In)
TB2-16,17              30   IOPort       PktUARTRX        0        RXData          (In)
TB2-18,19              31   IOPort       PktUARTTX        0        TXData          (Out)
Internal-TXEn          32   IOPort       PktUARTTX        0        TXEna           (Out)
Internal               33   IOPort       SSR              0        AC Ref          (Out)

IO Connections for P1 -> 7I96_2
Pin#                  I/O   Pri. func    Sec. func        Chan     Sec. Pin func   Sec. Pin Dir

P1-01/DB25-01          34   IOPort       SSerial          0        RXData4         (In)
P1-02/DB25-14          35   IOPort       SSerial          0        TXData4         (Out)
P1-03/DB25-02          36   IOPort       SSerial          0        RXData3         (In)
P1-04/DB25-15          37   IOPort       SSerial          0        TXData3         (Out)
P1-05/DB25-03          38   IOPort       SSerial          0        RXData2         (In)
P1-06/DB25-16          39   IOPort       SSerial          0        TXData2         (Out)
P1-07/DB25-04          40   IOPort       SSerial          0        RXData1         (In)
P1-08/DB25-17          41   IOPort       SSerial          0        TXData1         (Out)
P1-09/DB25-05          42   IOPort       SSerial          0        RXData0         (In)
P1-11/DB25-06          43   IOPort       SSerial          0        TXData0         (Out)
P1-13/DB25-07          44   IOPort       MuxedQCountSel   0        MuxSel0         (Out)
P1-15/DB25-08          45   IOPort       MuxedQCount      0        MuxQ-A          (In)
P1-17/DB25-09          46   IOPort       MuxedQCount      0        MuxQ-B          (In)
P1-19/DB25-10          47   IOPort       MuxedQCount      0        MuxQ-IDX        (In)
P1-21/DB25-11          48   IOPort       MuxedQCount      1        MuxQ-A          (In)
P1-23/DB25-12          49   IOPort       MuxedQCount      1        MuxQ-B          (In)
P1-25/DB25-13          50   IOPort       MuxedQCount      1        MuxQ-IDX        (In)
    

Please Log in or Create an account to join the conversation.

More
28 Dec 2025 15:18 #340621 by PCW
Replied by PCW on topic Bitfile for Mesa 7i96s + 7i85 (+Modbus (PKT-Pin))
Yes, you may need to use pkluart (RX and TX) version 2 if not running the latest LinuxCNC

Please Log in or Create an account to join the conversation.

Moderators: PCW, jmelson
  1. Hardware & Machines
  3. Driver Boards
  5. Bitfile for Mesa 7i96s + 7i85 (+Modbus (PKT-Pin))
Time to create page: 0.075 seconds
Powered by Kunena Forum