Mesa FW stack? 2*7i29 + 3*exe602e

Hello

In a configuration of a 7KW 400mm^3 mill with DC servos and Heidenhain glass scales, I can not determine with the available documentation if the configuration I have in mind is supported, or if there is a preferable alternative.

I'd like to do something like this

5i23

---

(2*7i29)

---

(7i37ta)

---

(7i47s)

(2*7i29)

---

> for the 3 axis dc-servos
(7i37ta)

---

> machine housekeeping, pumps, limits switches, &c.
(7i47s)

---

> reads the glass scales via exe-boxes + contols spindle motor.

Each glass scale has 4 outputs.
1,2 ) Incremental postion in quadrature (rs-422)
3) positional reference (rs-422)
4) fault (ttl compatible)

Is this a forseen application of the 7i47s? Does a firmware stack exist for this?

firmware=hm2/5i23/????

pncconf says:
"You are have no hostmot2 firmware downloaded in folder:/lib/firmware/hm2/"

find on git head says:
linux-cnc/git/emc2-dev-workdir $ find . -name \*firm\*
./src/hal/drivers/pluto_step_firmware
./src/hal/drivers/pluto_servo_firmware
./src/hal/drivers/mesa-hostmot2/firmware

but ./src/hal/drivers/mesa-hostmot2/firmware is basically empty.

Thanks
_jC
.

I dont think theres a standard bitfle (firmware) for this but
should be an easy custom config

(standard firmware needs to be downloaded separately from LinuxCNC via apt-get install hostmot2-firmware-5i23 )

Do you have the original (analog?) servo drives This would make things easier by allowing use of a 5I25/7I77

PCW wrote:

I dont think theres a standard bitfle (firmware) for this but
should be an easy custom config

(standard firmware needs to be downloaded separately from LinuxCNC via apt-get install hostmot2-firmware-5i23 )

The build system is monolithic, except when it isn't.

Do you have the original (analog?) servo drives This would make things easier by allowing use of a 5I25/7I77

This machine is of the vintage where there is a single servo-drive multiplexed amonst the 3-axis. Streckensteuerung.

The X& Y servos are 4,3Nm with 6,4Nm on the Z, so I thought the 7i29 looked like a good match, with an axis drive to spare. BTW, what would be a recommended back EMF filter? Vishay 4700UF200v are the best price point at Farnell. The 7i29 manual says "an output capacitor in the 5000 uF range for 2 motors when the 7I29 is operated at a nominal 165V", so I ass-u-me 2 such Vishays would be sufficient?

Thanks again
_jC
.

PCW wrote:

I dont think theres a standard bitfle (firmware) for this but
should be an easy custom config

OK. I'm moving _very_ slowly along.

I would now like to build a bitfile for my configuration. It seems the out-of-the-box bitfiles assign daughterboards to cables in a non-optimal way for me.

I have skimmed through the firmware sources and installed the xilinx 9.2i environment as described here:

My goal is to create a bitfile for the 5i23 with the following assignments:

i/o ...... mesacard
0-23 ..... 7i47s
24-47 .... 7i37
48-71 .... 2x7i29

The encoder ports of the 7i47s are wired to HH 602es, the isolated out and analog is wired to a Lenz DC motor control, the remaining rs422 pins are for future expansion.

The 7i37 is to replace the machines existing relay logic.

Hopefully I'll have the encoders bored out to 15mm next week to fit the old tacho shafts of the existing servos and be ready to test run the 7i29 units, but I would prefer to cable those cards to P4 of the 5i23.

So my question is, how does one go about creating a custom .vhd file with the wished for pin assignments. I'm looking at modifying PIN_SVST8_4IM2SI_72.vhd for example.

Further concrete questions. What is the naming convention for the PIN_ files. I've read in the documentation that SV and ST are servo and stepper respectively.

What do the name tags SP, SS, IM, SI, TP, TW and so on represent?

Is there a recipe or cook-book for putting together a custom .vhd file?

Thanks
.

andypugh wrote:

That sounds like one of the Firmwares from the Mesa site.

Naw, found that .vhd in the tree from 'apt-get source hostmot2-firmware-5i23'

Still, I am haveing what must be a very basic missunderstanding of the 'PinDesc' stanza of the PIN_x.vhd files.

This section seems like a direct mapping onto a 7i29 equivalent

IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 00
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 01
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 02
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 03
IOPortTag & x"01" & QCountTag & QCountIDXPin, -- I/O 04
IOPortTag & x"00" & QCountTag & QCountIDXPin, -- I/O 05
IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 06
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 07
IOPortTag & x"01" & PWMTag & PWMBDirPin, -- I/O 08
IOPortTag & x"00" & PWMTag & PWMBDirPin, -- I/O 09
IOPortTag & x"01" & PWMTag & PWMCEnaPin, -- I/O 10
IOPortTag & x"00" & PWMTag & PWMCEnaPin, -- I/O 11
IOPortTag & x"03" & QCountTag & QCountQBPin, -- I/O 12
IOPortTag & x"03" & QCountTag & QCountQAPin, -- I/O 37
IOPortTag & x"02" & QCountTag & QCountQBPin, -- I/O 14
IOPortTag & x"02" & QCountTag & QCountQAPin, -- I/O 15
IOPortTag & x"03" & QCountTag & QCountIDXPin, -- I/O 16
IOPortTag & x"02" & QCountTag & QCountIDXPin, -- I/O 17
IOPortTag & x"03" & PWMTag & PWMAOutPin, -- I/O 18
IOPortTag & x"02" & PWMTag & PWMAOutPin, -- I/O 19
IOPortTag & x"03" & PWMTag & PWMBDirPin, -- I/O 20
IOPortTag & x"02" & PWMTag & PWMBDirPin, -- I/O 21
IOPortTag & x"03" & PWMTag & PWMCEnaPin, -- I/O 22
IOPortTag & x"02" & PWMTag & PWMCenaPin, -- I/O 23

7i29 CONNECTORS (from manual v1.1)
CONTROLLER CONNECTOR
P5 is the motion controller connector P5 is a 50 pin latching header that mates with
standard female IDC headers.
PIN FUNCTION PIN FUNCTION
1 MOTOR1 ENCB
3 MOTOR1 ENCA
5 MOTOR0 ENCB
7 MOTOR0 ENCA
9 INDEX1
11 INDEX0
13 MOTOR1 PWM
15 MOTOR0 PWM
17 MOTOR1 DIR
19 MOTOR0 DIR
21 /MOTOR1 ENA
23 /MOTOR0 ENA
25 MOTOR3 ENCB
27 MOTOR3 ENCA
29 MOTOR2 ENCB
31 MOTOR2 ENCA
33 INDEX3
35 INDEX2
37 MOTOR3 PWM
39 MOTOR2 PWM
41 MOTOR3 DIR
43 MOTOR2 DIR
45 /MOTOR3 ENA
47 /MOTOR2 ENA

But if that is true, I have found nothing that matches up with the connector mapping of the 7i47S, especially as it is not clear at all how the assignment of the encoder phases and signals is to be made.

7i47
CONTROLLER CONNECTOR
50 pin header connector J1 connects to the anything I/O card/motion controller. This
can be a male 50 pin header on the top of the 7I47S card or a female 50 conductor header
on the bottom side of the 7I47S depending on 7I47S model.
PIN FUNCTION DIRECTION
1 TX4 TO 7I47S
3 TX5 TO 7I47S
5 TX6 TO 7I47S
7 TX7 TO 7I47S
9 RX0 FROM 7I47S
11 RX6 FROM 7I47S
13 RX1 FROM 7I47S
15 RX7 FROM 7I47S
17 RX2 FROM 7I47S
19 RX8 FROM 7I47S
21 RX3 FROM 7I47S
23 RX9 FROM 7I47S
25 RX4 FROM 7I47S
27 RX10 FROM 7I47S
29 RX5 FROM 7I47S
31 RX11 FROM 7I47S
33 AUX TO 7I47S
35 DIR TO 7I47S
37 /ENA TO 7I47S
39 PWM TO 7I47S
41 TX0 TO 7I47S
43 TX1 TO 7I47S
45 TX2 TO 7I47S
47 TX3 TO 7I47S


Maybe this from PIN_SV12_3X7I47_72.vhd ???
constant PinDesc : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"02" & PWMTag & PWMAOutPin, -- I/O 00
IOPortTag & x"02" & PWMTag & PWMBDirPin, -- I/O 01
IOPortTag & x"03" & PWMTag & PWMAOutPin, -- I/O 02
IOPortTag & x"03" & PWMTag & PWMBDirPin, -- I/O 03
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 04
IOPortTag & x"02" & QCountTag & QCountQAPin, -- I/O 05
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 06
IOPortTag & x"02" & QCountTag & QCountQBPin, -- I/O 07
IOPortTag & x"00" & QCountTag & QCountIDXPin, -- I/O 08
IOPortTag & x"02" & QCountTag & QCountIDXPin, -- I/O 09
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 10
IOPortTag & x"03" & QCountTag & QCountQAPin, -- I/O 11
IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 12
IOPortTag & x"03" & QCountTag & QCountQBPin, -- I/O 13
IOPortTag & x"01" & QCountTag & QCountIDXPin, -- I/O 14
IOPortTag & x"03" & QCountTag & QCountIDXPin, -- I/O 15
IOPortTag & x"00" & NullTag & x"00", -- I/O 16
IOPortTag & x"00" & NullTag & x"00", -- I/O 17
IOPortTag & x"00" & NullTag & x"00", -- I/O 18
IOPortTag & x"00" & NullTag & x"00", -- I/O 19
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 20
IOPortTag & x"00" & PWMTag & PWMBDirPin, -- I/O 21
IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 22
IOPortTag & x"01" & PWMTag & PWMBDirPin, -- I/O 23

Or this bit here from PIN_SVST2_4_7I47_72.vhd (as there is stepgen stuff where the analog motor control is on the 'S' version of this card, I'm guessing no).

constant PinDesc : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 00
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 01
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 02
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 03
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 04
IOPortTag & x"02" & QCountTag & QCountQAPin, -- I/O 05
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 06
IOPortTag & x"02" & QCountTag & QCountQBPin, -- I/O 07
IOPortTag & x"00" & QCountTag & QCountIDXPin, -- I/O 08
IOPortTag & x"02" & QCountTag & QCountIDXPin, -- I/O 09
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 10
IOPortTag & x"03" & QCountTag & QCountQAPin, -- I/O 11
IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 12
IOPortTag & x"03" & QCountTag & QCountQBPin, -- I/O 13
IOPortTag & x"01" & QCountTag & QCountIDXPin, -- I/O 14
IOPortTag & x"03" & QCountTag & QCountIDXPin, -- I/O 15
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 16
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 17
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 18
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 19
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 20
IOPortTag & x"00" & PWMTag & PWMBDirPin, -- I/O 21
IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 22
IOPortTag & x"01" & PWMTag & PWMBDirPin, -- I/O 23

what I've got for 7i47 templates:
sixis@sixis:~/hm2-firmware/hostmot2-firmware-0.8$ ls -l *47*
-rw-r--r-- 1 sixis sixis 10968 Dec 19 2010 PIN_SV12_3X7I47_72.vhd
-rw-r--r-- 1 sixis sixis 13300 Dec 19 2010 PIN_SVST12_12_2X7I48_2X7I47_96.vhd
-rw-r--r-- 1 sixis sixis 10898 Dec 19 2010 PIN_SVST1_4_7I47_72.vhd
-rw-r--r-- 1 sixis sixis 9784 Dec 19 2010 PIN_SVST2_4_7I47_48.vhd
-rw-r--r-- 1 sixis sixis 10829 Dec 19 2010 PIN_SVST2_4_7I47_72.vhd
-rw-r--r-- 1 sixis sixis 11877 Dec 19 2010 PIN_SVST2_4_7I47_96.vhd


Thanx again
jC

Getting closer

Made the following edits into PIN_SVST_FOOBAR.vhd

---

constant PinDesc : PinDescType :=(
-- Base func sec unit sec func sec pin
-- 7i47S
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 00
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 01
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 02
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 03
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 04
IOPortTag & x"02" & QCountTag & QCountQAPin, -- I/O 05
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 06
IOPortTag & x"02" & QCountTag & QCountQBPin, -- I/O 07
IOPortTag & x"00" & QCountTag & QCountIDXPin, -- I/O 08
IOPortTag & x"02" & QCountTag & QCountIDXPin, -- I/O 09
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 10
IOPortTag & x"03" & QCountTag & QCountQAPin, -- I/O 11
IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 12
IOPortTag & x"03" & QCountTag & QCountQBPin, -- I/O 13
IOPortTag & x"01" & QCountTag & QCountIDXPin, -- I/O 14
IOPortTag & x"03" & QCountTag & QCountIDXPin, -- I/O 15
IOPortTag & x"00" & NullTag & x"00", -- I/O 16 7I47S SPARE ISOLATED OUT
IOPortTag & x"00" & PWMTag & PWMBDirPin, -- I/O 17 7I47S DIRECTION
IOPortTag & x"00" & PWMTag & PWMCEnaPin, -- I/O 18 7I47S PWMENABLE
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 19 7I47S PWMOUT
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 20
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 21
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 22
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 23
-- 7i37
IOPortTag & x"00" & NullTag & x"00", -- I/O 24
IOPortTag & x"00" & NullTag & x"00", -- I/O 25
IOPortTag & x"00" & NullTag & x"00", -- I/O 26
IOPortTag & x"00" & NullTag & x"00", -- I/O 27
IOPortTag & x"00" & NullTag & x"00", -- I/O 28
IOPortTag & x"00" & NullTag & x"00", -- I/O 29
IOPortTag & x"00" & NullTag & x"00", -- I/O 30
IOPortTag & x"00" & NullTag & x"00", -- I/O 31
IOPortTag & x"00" & NullTag & x"00", -- I/O 32
IOPortTag & x"00" & NullTag & x"00", -- I/O 33
IOPortTag & x"00" & NullTag & x"00", -- I/O 34
IOPortTag & x"00" & NullTag & x"00", -- I/O 35
IOPortTag & x"00" & NullTag & x"00", -- I/O 36
IOPortTag & x"00" & NullTag & x"00", -- I/O 37
IOPortTag & x"00" & NullTag & x"00", -- I/O 38
IOPortTag & x"00" & NullTag & x"00", -- I/O 39
IOPortTag & x"00" & NullTag & x"00", -- I/O 40
IOPortTag & x"00" & NullTag & x"00", -- I/O 41
IOPortTag & x"00" & NullTag & x"00", -- I/O 42
IOPortTag & x"00" & NullTag & x"00", -- I/O 43
IOPortTag & x"00" & NullTag & x"00", -- I/O 44
IOPortTag & x"00" & NullTag & x"00", -- I/O 45
IOPortTag & x"00" & NullTag & x"00", -- I/O 46
IOPortTag & x"00" & NullTag & x"00", -- I/O 47

-- 2x 7i29
IOPortTag & x"05" & QCountTag & QCountQBPin, -- I/O 48
IOPortTag & x"05" & QCountTag & QCountQAPin, -- I/O 49
IOPortTag & x"04" & QCountTag & QCountQBPin, -- I/O 50
IOPortTag & x"04" & QCountTag & QCountQAPin, -- I/O 51
IOPortTag & x"05" & QCountTag & QCountIDXPin, -- I/O 52
IOPortTag & x"04" & QCountTag & QCountIDXPin, -- I/O 53
IOPortTag & x"05" & PWMTag & PWMAOutPin, -- I/O 54
IOPortTag & x"04" & PWMTag & PWMAOutPin, -- I/O 55
IOPortTag & x"05" & PWMTag & PWMBDirPin, -- I/O 56
IOPortTag & x"04" & PWMTag & PWMBDirPin, -- I/O 57
IOPortTag & x"05" & PWMTag & PWMCEnaPin, -- I/O 58
IOPortTag & x"04" & PWMTag & PWMCEnaPin, -- I/O 59
IOPortTag & x"07" & QCountTag & QCountQBPin, -- I/O 60
IOPortTag & x"07" & QCountTag & QCountQAPin, -- I/O 61
IOPortTag & x"06" & QCountTag & QCountQBPin, -- I/O 62
IOPortTag & x"06" & QCountTag & QCountQAPin, -- I/O 63
IOPortTag & x"07" & QCountTag & QCountIDXPin, -- I/O 64
IOPortTag & x"06" & QCountTag & QCountIDXPin, -- I/O 65
IOPortTag & x"07" & PWMTag & PWMAOutPin, -- I/O 66
IOPortTag & x"06" & PWMTag & PWMAOutPin, -- I/O 67
IOPortTag & x"07" & PWMTag & PWMBDirPin, -- I/O 68
IOPortTag & x"06" & PWMTag & PWMBDirPin, -- I/O 69
IOPortTag & x"07" & PWMTag & PWMCEnaPin, -- I/O 70
IOPortTag & x"06" & PWMTag & PWMCEnaPin, -- I/O 71

emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,

emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);

end package PIN_SVST_FOOBAR;

---

Looks good until:

All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
constraint does not cover any paths or that it has no requested value.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 mins 4 secs
Total CPU time to PAR completion: 2 mins 2 secs

Peak Memory Usage: 168 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 2
Number of info messages: 0

Writing design to file work.ncd



PAR done!
# exited with 0
# bitgen -w -g 'DONE_cycle:6' -g 'GWE_cycle:4' -g 'GTS_cycle:5' -g 'LCK_cycle:NoWait' work.ncd work.bit work.pcf
Release 9.2.04i - Bitgen J.36
Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '3s400.nph' in environment
/home/sixis/xilinx/Xilinx92i.
"top" is an NCD, version 3.1, device xc3s400, package pq208, speed -5
Opened constraints file work.pcf.

Sun Aug 26 16:35:24 2012

Running DRC.
INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
with the CLKFX and CLKFX180 outputs of the DCM comp ClockMult/ClockMult,
consult the device Interactive Data Sheet.
DRC detected 0 errors and 0 warnings.
Creating bit map...
Saving bit stream in "work.bit".
Bitstream generation is complete.
# exited with 0
2:18.9-xst 0:08.2-ngdbuild 0:20.8-map 2:08.3-par 0:18.0-bitgen
./pin.py SVST_FOOBAR i23 > fw/5i23/SVST_FOOBAR.PIN.tmp
# tempdir /tmp/hm2fGSJD8
# ghdl -a -fexplicit '--ieee=synopsys' IDROMConst.vhd idrom_tools.vhd PIN_SVST_FOOBAR.vhd i23card.vhd pinmaker_SVST_FOOBAR.vhd
# exited with 127
make: *** [fw/5i23/SVST_FOOBAR.PIN] Error 127
sixis@sixis:~/hm2-firmware/hostmot2-firmware-0.8$

Hmmm???

Edit

Nevermind. Package 'ghdl' has to be held so that apt doesn't remove it due to stale dependancies.

Edit^2

Voila!
sixis@sixis:~/hm2-firmware/hostmot2-firmware-0.8$ make
+ make
./pin.py SVST_FOOBAR i23 > fw/5i23/SVST_FOOBAR.PIN.tmp
# tempdir /tmp/hm2J0Yhpe
# ghdl -a -fexplicit '--ieee=synopsys' IDROMConst.vhd idrom_tools.vhd PIN_SVST_FOOBAR.vhd i23card.vhd pinmaker_SVST_FOOBAR.vhd
# exited with 0
# ghdl -e -fexplicit '--ieee=synopsys' pinmaker_SVST_FOOBAR
# exited with 0
# ghdl -r pinmaker_SVST_FOOBAR
# exited with 0
mv fw/5i23/SVST_FOOBAR.PIN.tmp fw/5i23/SVST_FOOBAR.PIN
./pinxml.py SVST_FOOBAR i23 > fw/5i23/SVST_FOOBAR.xml.tmp
# tempdir /tmp/hm2dsjH3c
# ghdl -a -fexplicit '--ieee=synopsys' IDROMConst.vhd idrom_tools.vhd PIN_SVST_FOOBAR.vhd i23card.vhd xmlrom_SVST_FOOBAR.vhd
# exited with 0
# ghdl -e -fexplicit '--ieee=synopsys' xmlrom_SVST_FOOBAR
# exited with 0
# ghdl -r xmlrom_SVST_FOOBAR
# exited with 0
mv fw/5i23/SVST_FOOBAR.xml.tmp fw/5i23/SVST_FOOBAR.xml