PC doesn't boot after plug in 6i25 Mesa card

30 Mar 2018 12:26 - 30 Mar 2018 12:26 #108105 by CERTIA
Hello everyone,

I have an issue with my card. I load a simple code that turns ON the USER1 green LED with the terminal in LinuxCNC (I did the bitfile with Xilinx on Windows, file.txt attached). (The bitfile is in .txt to be uploaded.)

mesaflash --device 5i25 --write df_v1.bit
mesaflash --device 5i25 --reload

After these lines, one red LED (I think /DONE) was ON then OFF and my green LED was ON.
Then I misscliked and redo mesaflash --device 5i25 --write df_v1.bit This is at this moment that my PC froze.
Nothing happened so I turned it OFF. When I retry to turn ON the PC, my screen did not start, but the code was still inside the card because the green LED was ON. Before that, the 2 red LEDS were ON then only the /Done LED. Since my screen still did not start, I turned it back OFF. At this moment, the 2 red LEDS were ON very quickly then OFF. Just a few secondes after, it did the same lightnings as before the green LED was ON (/DONE + INIT ---> then just /DONE).

I work with a 6i25 Superport FPGA (Spartan 6 / LX9 / TQG144 / PCIE). Computer details attached.

Can you help me solve this problem or give me advices please?

Thanks in advance.

Last edit: 30 Mar 2018 12:26 by CERTIA.
30 Mar 2018 15:04 #108109 by PCW
This is pretty much expected, if you write a random bitfile to the 6I25, it has about a 99% chance of interfering with the PCs bus interface, and hanging the PC

You can recover by

1. Using a JTAG programmer to put a working bitfile in the flash chip
2. Preventing the flash load at power-up and reprogramming the flash using mesaflashes --recover option
(you can disable the flash load at power-up by (carefully) shorting U2 pins 1 and 2 when you power-up the PC)

To avoid doing this again I would suggest writing test configurations to the fallback area of the flash memory:

sudo mesaflash --device 5i25 --write funkyfile.bit --fallback (write test program to fallback area of flash)
sudo mesaflash --device 5i25 --reload --fallback (load FPGA from fallback area of flash)

Then if you have a problem with the program in the fallback area, you can recover by power
cycling the PC (assuming you have a good user configuration in the flash)
The following user(s) said Thank You: tivoi, CERTIA
30 Mar 2018 15:29 #108110 by CERTIA
Thanks for your reply PCW,

I thought it was the end... But how do you use a JTAG programmer to put the working bitfile please ?
For the working bitfile, can I use like 5i25_7i77x2.bit (in hostmot2 folder, attached) ?
What are the "U2 pins 1 and 2" please ?

Thanks in advance.

30 Mar 2018 16:37 #108112 by PCW
The Xilinx tools to not make programming the flash chip easy, you need to create a prom format file (bitfiles dont work)

U2 is the flash chip on the 6I25 (upper right corner of card)
The following user(s) said Thank You: CERTIA
16 Apr 2018 09:48 - 16 Apr 2018 09:49 #109119 by CERTIA
Hello PCW,

I generated a prom with IMPACT (attached screens). I don't know if I did it correctly... Can you tell me if a 4-pins JTAG is enough to debug the card or do I need a 6-pins cable? I tried to make a cable out of two (because I don't have any). I soldered the pins like:
USB 6I25
Data- TDO
Data+ TDI
But it does not work, I think I need 6 pins but how do we solder the pins to the USB connector please?

Thanks in advance.

Last edit: 16 Apr 2018 09:49 by CERTIA.
16 Apr 2018 13:58 #109121 by PCW
Typically the power pin on the JTAG connector is used to set the
input and output voltage levels of the JTAG programming cable.
Its definitely needed for for the Xilinx cables I am familiar with
16 Apr 2018 14:11 #109122 by CERTIA
Or can you tell me what kind of cable should I buy? (I remind you that I work with a 6i25 Superport FPGA)
16 Apr 2018 14:59 #109125 by PCW
I have been using a Digilent HS2 cable, It definitely requires a VCC pin to determine the I/O levels
The following user(s) said Thank You: CERTIA
17 Apr 2018 08:45 #109174 by CERTIA
Ok, do you think that I can create a JTAG using only fours wires for TDI, TDO, GND and 3.3V? (It seems that there is some electronic between the FPGA connector to the USB one)

If not I will wait to receive a Diligent HS2 cable (is there another type of cable that would work as well?)
Finally, can you tell me if my screenshots are correct please? Else, what should I do ?

Thanks in advance PCW.

17 Apr 2018 14:35 #109187 by PCW
As far as I know you need all 6 wires for Xilinx and the JTAG cables I use.

Its possible you could get by with 5 wires (no 3.3V) on a JTAG cable that
had fixed output voltages (and that you setup for 3.3V signaling)
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