Interfacing mesa 7i92T and Keling KL-6050 drive

Hi everybody,
I been using Mach3 and a Chinese BOB for couple of years. I decided to move up to the next step, LinuxCNC and Mesa board. I picked up a 7i92TF,  planning to use it with my existent BOB. But reading through this forum, i decided to connect directly (if it is possible) the Mesa 7i92T to my Keling KL-6050 drives. According to the manual, "To allow interfacing with 5V inputs, the 7I92T has bus switches on all I/O pins. The bus switches work by turning off when the input voltage exceeds a preset threshold. The bus switches also allow the I/O pins to be pulled up to 5V when used as inputs or outputs in the open drain mode." Getting familiar with "open drain mode", pull-up resistor and push-pull CMOS, I am guessing that to connect an IO from 7i92T to an input signal on KL-6050 it should look like in the attached image. 
Could you please confirm if this schematic is correct? 
What is the preset threshold  value of the input voltage on the IO of the 7i92T?

Thank you. 

The default input threshold is a standard
TTL threshold level of about 1.6V.

The 7I92T can have pullups or pulldowns
but since the open drain mode only sinks,
if you want to drive OPTOS with anodes
referenced to 5V, you need to use the
pullup option. In this case, you would also
invert the step/dir outputs since they are active
low with this wiring.

Thank you gentlemen for your fast reply. If I understand it right, this is one option of connectivity, the other one will be with the OPTOS having the cathodes referenced to the ground, and the IO's from Mesa connected to STEP+, DIR+, like in the attached picture, am I right? 
But I am very confused with what the manual says: "Note that even though the 7I92T can tolerate 5V signal inputs, its outputs will not
swing to 5V. The outputs are push pull CMOS that will drive to the output supply rail of 3.3V. This is sufficient for TTL compatibility but may cause problems with some types of loads. For example when driving an LED that has its anode connected to 5V, in such devices as OPTO isolators and I/O module rack SSRs, the 3.3V high level may not completely turn the LED off. To avoid this problem, either drive loads that are ground referred, Use 3.3V as the VCC for VCC referred loads, or use open drain mode."

Since the STEP + and DIR + on the KL-6050 drive requests 4-5V for HIGH and 0-0.5V for LOW and a typical current of 10mA, my questions are: are these types of interconnection correct to drive the load with no issues? Are the pull-ups resistors internally connected to 5V or to 3.3V when W1 and W2 are UP? 

The only way to get full 5V drive (into any significant load)
from the bare  7I92T FPGA outputs is to use sinking outputs
(active low) and return the drive common to +5V. When
this is done (and opendrain mode is enabled in the hal file)
The outputs will swing up to 5V when off (with no load current)
and pull down to 0V when on, so you get a full 5V swing
(- some saturation resistance*10 mA ~= 0.2V)

The pullups on a 7I92T are connected to +5V

If you use active high outputs you only get significant drive
up to 3.3V (the 4.7K pullups to 5V wont help much)

Thank you Peter, for clarifications! So my first approach is the right one, correct?
How to enable open drain in the hal file? By inverting the pin? Or is it something else?

Output pins have invert and opendrain parameters, for example:

hm2_7i92.0.stepgen.00.direction.invert_output
hm2_7i92.0.stepgen.00.direction.is_opendrain
hm2_7i92.0.stepgen.00.step.invert_output
hm2_7i92.0.stepgen.00.step.is_opendrain

Thank you!