Mesa 7I92TM Parallel port pin mapping

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13 Aug 2024 16:58 #307641 by DougM
in PNCConf how do I assign a StepGen to the specific pins on the parallel port?

Background
I found myself with a K2 CNC router.  The parallel pinouts are non-standard

I was able to get it working in StepConf on an old machine with a built-in parallel port, but I wanted to get it running under the 7i92TM.  I have 2 other machines running with these cards.  I configured the card and cold-swapped it into one of the other machines and it worked perfectly.

But I must have just gotten lucky and the pin mappings were magically perfect on those other two machines because I can't find anywhere where I can assign the pins to the axes in PNCCONF.

I think it should be P2 on the attached PNG file, but on the far left column it says, "Num" 0, 1 and 2 and it assigns those to the stepgen.

But I can't figure out how to configure the StepGen to the specific pins.

I know it's some simple step I missed, but I'm totally wrapped around the axle on this.

Thank you,

 
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13 Aug 2024 17:33 #307643 by PCW
Replied by PCW on topic Mesa 7I92TM Parallel port pin mapping
You cannot change the pinout of a specific firmware, you need
to choose firmware that matches the breakout you use.
You can change which stepgen runs which motion axis.

What breakout board do you need to support? For most
breakouts there are specific firmware files that match
their pinouts.

You can check pinouts by looking at the .pin files in the 7I92.zip
firmware distribution zip file (in /configs/hostmot2)

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13 Aug 2024 18:34 #307647 by DougM
Replied by DougM on topic Mesa 7I92TM Parallel port pin mapping
There is no breakout board - the K2 has a control box with a DB25F on the back. I could probably crack it open and see what it's running inside. From there I could likely re-route the lines to bring it back to "standard" pinouts. But it feels like this should be a .hal thing.

When you say "choose firmware" do you mean the firmware on the Mesa card?

Is this something I can configure via the Mesa Configuration Tool?

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13 Aug 2024 19:00 - 13 Aug 2024 19:00 #307650 by PCW
Replied by PCW on topic Mesa 7I92TM Parallel port pin mapping
In this case the control box contains the breakout board

There is no need to re-route signals, you just need firmware that
matches the required pinout.

Firmware is updated with the mesaflash tool, but the first step
is to determine the required pinout of your breakout

Do you have this pinout available?

(a working hal file created with stepconf would include this information)
 
Last edit: 13 Aug 2024 19:00 by PCW.

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13 Aug 2024 21:55 - 13 Aug 2024 22:02 #307668 by DougM
Replied by DougM on topic Mesa 7I92TM Parallel port pin mapping
Yes, I do.

X Step 4
X Dir 5
Y Step 2
Y Dir 3
Z Step 6
Z Dir 7

X Home 12
Y Home 11
Z Home 13

E-stop 10

Is the next step finding firmware that happens to match the above?  Or can I use the tool to poke the values into the right place, maybe using

--wpo     address value          Write hostmot2 variable directly at 'address' with 'value'.

Thanks so much for your guidance!
 
Last edit: 13 Aug 2024 22:02 by DougM.

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13 Aug 2024 22:04 - 13 Aug 2024 22:04 #307670 by PCW
Replied by PCW on topic Mesa 7I92TM Parallel port pin mapping
7i92t_5abobx2d.bin should work with:

Stepgen0 --> Y axis
Stepgen1 --> X axis
Stepgen2 --> Z axis

Also in pncconf, set the number of stepgens to 3,
and the number of pwmgens and encoders to 0 to
free up the other pins so they can be used as
GPIO if needed.

 
Last edit: 13 Aug 2024 22:04 by PCW.

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16 Aug 2024 16:16 - 16 Aug 2024 16:18 #307938 by DougM
Replied by DougM on topic Mesa 7I92TM Parallel port pin mapping
Successfully flashed 7i92t_5abobx2d.bin onto the MESA card (and performed a reload).

Here is the output of readhmid:
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Configuration Name: HOSTMOT2

General configuration information:

BoardName : MESA7I92
FPGA Size: 20 KGates
FPGA Pins: 256
Number of IO Ports: 2
Width of one I/O port: 17
Clock Low frequency: 100.0000 MHz
Clock High frequency: 180.0000 MHz
IDROM Type: 3
Instance Stride 0: 4
Instance Stride 1: 64
Register Stride 0: 256
Register Stride 1: 256

Modules in configuration:

Module: DPLL
There are 1 of DPLL in configuration
Version: 0
Registers: 7
BaseAddress: 7000
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes

Module: WatchDog
There are 1 of WatchDog in configuration
Version: 0
Registers: 3
BaseAddress: 0C00
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes

Module: IOPort
There are 2 of IOPort in configuration
Version: 0
Registers: 5
BaseAddress: 1000
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes

Module: QCount
There are 2 of QCount in configuration
Version: 2
Registers: 5
BaseAddress: 3000
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes

Module: StepGen
There are 10 of StepGen in configuration
Version: 2
Registers: 10
BaseAddress: 2000
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes

Module: PWM
There are 2 of PWM in configuration
Version: 0
Registers: 5
BaseAddress: 4100
ClockFrequency: 180.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes

Module: LED
There are 1 of LED in configuration
Version: 0
Registers: 1
BaseAddress: 0200
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes

Configuration pin-out:

IO Connections for P2
DB25 pin# I/O Pri. func Sec. func Chan Sec. Pin func Sec. Pin Dir

1 0 IOPort PWM 0 PWM (Out)
14 1 IOPort None
2 2 IOPort StepGen 0 Step/Table1 (Out)
15 3 IOPort None
3 4 IOPort StepGen 0 Dir/Table2 (Out)
16 5 IOPort StepGen 8 Step/Table1 (Out)
4 6 IOPort StepGen 1 Step/Table1 (Out)
17 7 IOPort StepGen 8 Dir/Table2 (Out)
5 8 IOPort StepGen 1 Dir/Table2 (Out)
6 9 IOPort StepGen 2 Step/Table1 (Out)
7 10 IOPort StepGen 2 Dir/Table2 (Out)
8 11 IOPort StepGen 3 Step/Table1 (Out)
9 12 IOPort StepGen 3 Dir/Table2 (Out)
10 13 IOPort None
11 14 IOPort QCount 0 Quad-A (In)
12 15 IOPort QCount 0 Quad-B (In)
13 16 IOPort QCount 0 Quad-IDX (In)

IO Connections for P1
DB25 pin# I/O Pri. func Sec. func Chan Sec. Pin func Sec. Pin Dir

1 17 IOPort PWM 1 PWM (Out)
14 18 IOPort None
2 19 IOPort StepGen 4 Step/Table1 (Out)
15 20 IOPort None
3 21 IOPort StepGen 4 Dir/Table2 (Out)
16 22 IOPort StepGen 9 Step/Table1 (Out)
4 23 IOPort StepGen 5 Step/Table1 (Out)
17 24 IOPort StepGen 9 Dir/Table2 (Out)
5 25 IOPort StepGen 5 Dir/Table2 (Out)
6 26 IOPort StepGen 6 Step/Table1 (Out)
7 27 IOPort StepGen 6 Dir/Table2 (Out)
8 28 IOPort StepGen 7 Step/Table1 (Out)
9 29 IOPort StepGen 7 Dir/Table2 (Out)
10 30 IOPort None
11 31 IOPort QCount 1 Quad-A (In)
12 32 IOPort QCount 1 Quad-B (In)
13 33 IOPort QCount 1 Quad-IDX (In)
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and here is the current HAL file (after manual edits for num_encoders, num_stepgens and num_pwmgens)
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# Generated by PNCconf at Fri Aug 16 08:59:19 2024
# Using LinuxCNC version: Master (2.9)
# If you make changes to this file, they will be
# overwritten when you run PNCconf again

loadrt [KINS]KINEMATICS
loadrt [EMCMOT]EMCMOT servo_period_nsec=[EMCMOT]SERVO_PERIOD num_joints=[KINS]JOINTS
loadrt hostmot2
loadrt hm2_eth board_ip="10.10.10.10" config="num_encoders=2 num_pwmgens=0 num_stepgens=3 sserial_port_0=00xxxxxx"
setp hm2_7i92.0.watchdog.timeout_ns 5000000
loadrt pid names=pid.x,pid.y,pid.z,pid.s

addf hm2_7i92.0.read servo-thread
addf motion-command-handler servo-thread
addf motion-controller servo-thread
addf pid.x.do-pid-calcs servo-thread
addf pid.y.do-pid-calcs servo-thread
addf pid.z.do-pid-calcs servo-thread
addf pid.s.do-pid-calcs servo-thread
addf hm2_7i92.0.write servo-thread
setp hm2_7i92.0.dpll.01.timer-us -50
setp hm2_7i92.0.stepgen.timer-number 1

# external output signals


# external input signals


#*******************
# AXIS X JOINT 0
#*******************

setp pid.x.Pgain [JOINT_0]P
setp pid.x.Igain [JOINT_0]I
setp pid.x.Dgain [JOINT_0]D
setp pid.x.bias [JOINT_0]BIAS
setp pid.x.FF0 [JOINT_0]FF0
setp pid.x.FF1 [JOINT_0]FF1
setp pid.x.FF2 [JOINT_0]FF2
setp pid.x.deadband [JOINT_0]DEADBAND
setp pid.x.maxoutput [JOINT_0]MAX_OUTPUT
setp pid.x.error-previous-target true
# This setting is to limit bogus stepgen
# velocity corrections caused by position
# feedback sample time jitter.
setp pid.x.maxerror 0.000500

net x-index-enable => pid.x.index-enable
net x-enable => pid.x.enable
net x-pos-cmd => pid.x.command
net x-pos-fb => pid.x.feedback
net x-output <= pid.x.output

# Step Gen signals/setup

setp hm2_7i92.0.stepgen.01.dirsetup [JOINT_0]DIRSETUP
setp hm2_7i92.0.stepgen.01.dirhold [JOINT_0]DIRHOLD
setp hm2_7i92.0.stepgen.01.steplen [JOINT_0]STEPLEN
setp hm2_7i92.0.stepgen.01.stepspace [JOINT_0]STEPSPACE
setp hm2_7i92.0.stepgen.01.position-scale [JOINT_0]STEP_SCALE
setp hm2_7i92.0.stepgen.01.step_type 0
setp hm2_7i92.0.stepgen.01.control-type 1
setp hm2_7i92.0.stepgen.01.maxaccel [JOINT_0]STEPGEN_MAXACCEL
setp hm2_7i92.0.stepgen.01.maxvel [JOINT_0]STEPGEN_MAXVEL

# ---closedloop stepper signals---

net x-pos-cmd <= joint.0.motor-pos-cmd
net x-vel-cmd <= joint.0.vel-cmd
net x-output => hm2_7i92.0.stepgen.01.velocity-cmd
net x-pos-fb <= hm2_7i92.0.stepgen.01.position-fb
net x-pos-fb => joint.0.motor-pos-fb
net x-enable <= joint.0.amp-enable-out
net x-enable => hm2_7i92.0.stepgen.01.enable

# ---setup home / limit switch signals---

net x-home-sw => joint.0.home-sw-in
net x-neg-limit => joint.0.neg-lim-sw-in
net x-pos-limit => joint.0.pos-lim-sw-in

#*******************
# AXIS Y JOINT 1
#*******************

setp pid.y.Pgain [JOINT_1]P
setp pid.y.Igain [JOINT_1]I
setp pid.y.Dgain [JOINT_1]D
setp pid.y.bias [JOINT_1]BIAS
setp pid.y.FF0 [JOINT_1]FF0
setp pid.y.FF1 [JOINT_1]FF1
setp pid.y.FF2 [JOINT_1]FF2
setp pid.y.deadband [JOINT_1]DEADBAND
setp pid.y.maxoutput [JOINT_1]MAX_OUTPUT
setp pid.y.error-previous-target true
# This setting is to limit bogus stepgen
# velocity corrections caused by position
# feedback sample time jitter.
setp pid.y.maxerror 0.000500

net y-index-enable => pid.y.index-enable
net y-enable => pid.y.enable
net y-pos-cmd => pid.y.command
net y-pos-fb => pid.y.feedback
net y-output <= pid.y.output

# Step Gen signals/setup

setp hm2_7i92.0.stepgen.00.dirsetup [JOINT_1]DIRSETUP
setp hm2_7i92.0.stepgen.00.dirhold [JOINT_1]DIRHOLD
setp hm2_7i92.0.stepgen.00.steplen [JOINT_1]STEPLEN
setp hm2_7i92.0.stepgen.00.stepspace [JOINT_1]STEPSPACE
setp hm2_7i92.0.stepgen.00.position-scale [JOINT_1]STEP_SCALE
setp hm2_7i92.0.stepgen.00.step_type 0
setp hm2_7i92.0.stepgen.00.control-type 1
setp hm2_7i92.0.stepgen.00.maxaccel [JOINT_1]STEPGEN_MAXACCEL
setp hm2_7i92.0.stepgen.00.maxvel [JOINT_1]STEPGEN_MAXVEL

# ---closedloop stepper signals---

net y-pos-cmd <= joint.1.motor-pos-cmd
net y-vel-cmd <= joint.1.vel-cmd
net y-output => hm2_7i92.0.stepgen.00.velocity-cmd
net y-pos-fb <= hm2_7i92.0.stepgen.00.position-fb
net y-pos-fb => joint.1.motor-pos-fb
net y-enable <= joint.1.amp-enable-out
net y-enable => hm2_7i92.0.stepgen.00.enable

# ---setup home / limit switch signals---

net y-home-sw => joint.1.home-sw-in
net y-neg-limit => joint.1.neg-lim-sw-in
net y-pos-limit => joint.1.pos-lim-sw-in

#*******************
# AXIS Z JOINT 2
#*******************

setp pid.z.Pgain [JOINT_2]P
setp pid.z.Igain [JOINT_2]I
setp pid.z.Dgain [JOINT_2]D
setp pid.z.bias [JOINT_2]BIAS
setp pid.z.FF0 [JOINT_2]FF0
setp pid.z.FF1 [JOINT_2]FF1
setp pid.z.FF2 [JOINT_2]FF2
setp pid.z.deadband [JOINT_2]DEADBAND
setp pid.z.maxoutput [JOINT_2]MAX_OUTPUT
setp pid.z.error-previous-target true
# This setting is to limit bogus stepgen
# velocity corrections caused by position
# feedback sample time jitter.
setp pid.z.maxerror 0.000500

net z-index-enable => pid.z.index-enable
net z-enable => pid.z.enable
net z-pos-cmd => pid.z.command
net z-pos-fb => pid.z.feedback
net z-output <= pid.z.output

# Step Gen signals/setup

setp hm2_7i92.0.stepgen.02.dirsetup [JOINT_2]DIRSETUP
setp hm2_7i92.0.stepgen.02.dirhold [JOINT_2]DIRHOLD
setp hm2_7i92.0.stepgen.02.steplen [JOINT_2]STEPLEN
setp hm2_7i92.0.stepgen.02.stepspace [JOINT_2]STEPSPACE
setp hm2_7i92.0.stepgen.02.position-scale [JOINT_2]STEP_SCALE
setp hm2_7i92.0.stepgen.02.step_type 0
setp hm2_7i92.0.stepgen.02.control-type 1
setp hm2_7i92.0.stepgen.02.maxaccel [JOINT_2]STEPGEN_MAXACCEL
setp hm2_7i92.0.stepgen.02.maxvel [JOINT_2]STEPGEN_MAXVEL

# ---closedloop stepper signals---

net z-pos-cmd <= joint.2.motor-pos-cmd
net z-vel-cmd <= joint.2.vel-cmd
net z-output => hm2_7i92.0.stepgen.02.velocity-cmd
net z-pos-fb <= hm2_7i92.0.stepgen.02.position-fb
net z-pos-fb => joint.2.motor-pos-fb
net z-enable <= joint.2.amp-enable-out
net z-enable => hm2_7i92.0.stepgen.02.enable

# ---setup home / limit switch signals---

net z-home-sw => joint.2.home-sw-in
net z-neg-limit => joint.2.neg-lim-sw-in
net z-pos-limit => joint.2.pos-lim-sw-in


#******************************
# connect miscellaneous signals
#******************************

# ---HALUI signals---

net axis-select-x halui.axis.x.select
net jog-x-pos halui.axis.x.plus
net jog-x-neg halui.axis.x.minus
net jog-x-analog halui.axis.x.analog
net x-is-homed halui.joint.0.is-homed
net axis-select-y halui.axis.y.select
net jog-y-pos halui.axis.y.plus
net jog-y-neg halui.axis.y.minus
net jog-y-analog halui.axis.y.analog
net y-is-homed halui.joint.1.is-homed
net axis-select-z halui.axis.z.select
net jog-z-pos halui.axis.z.plus
net jog-z-neg halui.axis.z.minus
net jog-z-analog halui.axis.z.analog
net z-is-homed halui.joint.2.is-homed
net jog-selected-pos halui.axis.selected.plus
net jog-selected-neg halui.axis.selected.minus
net spindle-manual-cw halui.spindle.0.forward
net spindle-manual-ccw halui.spindle.0.reverse
net spindle-manual-stop halui.spindle.0.stop
net machine-is-on halui.machine.is-on
net jog-speed halui.axis.jog-speed
net MDI-mode halui.mode.is-mdi

# ---coolant signals---

net coolant-mist <= iocontrol.0.coolant-mist
net coolant-flood <= iocontrol.0.coolant-flood

# ---probe signal---

net probe-in => motion.probe-input

# ---motion control signals---

net in-position <= motion.in-position
net machine-is-enabled <= motion.motion-enabled

# ---digital in / out signals---

# ---estop signals---

net estop-out <= iocontrol.0.user-enable-out
net estop-out => iocontrol.0.emc-enable-in

# ---manual tool change signals---

net tool-change-request <= iocontrol.0.tool-change
net tool-change-confirmed => iocontrol.0.tool-changed
net tool-number <= iocontrol.0.tool-prep-number

# ---Use external manual tool change dialog---

loadusr -W hal_manualtoolchange
net tool-change-request => hal_manualtoolchange.change
net tool-change-confirmed <= hal_manualtoolchange.changed
net tool-number => hal_manualtoolchange.number

# ---ignore tool prepare requests---
net tool-prepare-loopback iocontrol.0.tool-prepare => iocontrol.0.tool-prepared
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I still get no movement in any of the axes.  I wonder if there's something I am not properly enabling?  I didn't setup the Home or e-stop signals.

Thank you for your continued assistance,

 
Last edit: 16 Aug 2024 16:18 by DougM. Reason: add reload comment

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16 Aug 2024 16:24 #307940 by PCW
Replied by PCW on topic Mesa 7I92TM Parallel port pin mapping
Most common reason for lack of step/dir motion
is too short step lengths, So you might try doubling
those. Also check that the direction pin  to the step drive
changes state when jogging in either direction to verify
that the pinout is correct and that the  breakout board is
working as  expected.

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21 Aug 2024 16:50 - 21 Aug 2024 16:50 #308316 by DougM
Replied by DougM on topic Mesa 7I92TM Parallel port pin mapping
Can you tell me what the name of the factory firmware is (.bin)?

I want to start all over again.

Also, is there somewhere that explains the difference between a .bin, .bit and .pin files?

Thank you,
Last edit: 21 Aug 2024 16:50 by DougM.

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21 Aug 2024 17:13 #308322 by PCW
Replied by PCW on topic Mesa 7I92TM Parallel port pin mapping
You just need to select firmware that matches your breakout.
The original firmware not really relevant, its just there to allow
access to the card for re-flashing to the desired firmware.

.pin files are just text file that list the included firmware modules
and the pinout of a specific firmware. These are created with
mesaflash and can be used to check firmware compatibility
with a given breakout.

.bit files are firmware files for Xilinx based FPGA cards

.bin files are firmware files for Efinix based FPGA cards

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