Does 7i76e + 7i78 + 7i85 need a custom bin file?

Hi All, 

I'm trying to add a 7i78 and 7i85 card to P1 and P2 of my 7i76e. 
When I plug the 7i78 into P1 and mesaflash --readhmid, the usual 7i76e pins show up "on card" and I also get a list of the 7i78 pins on the "IO Connections for P1" list, an encoder and some stepgens, so that looks positive.

However I connected a bunch of test nets in my hal file, something like this but I'm not by the machine and the SSH isn't connecting now so I can't check: 
net test017 <= hm2_7i76e.0.7i76.0.0.input-17
net test018 <= hm2_7i76e.0.7i76.0.0.input-18
net test019 <= hm2_7i76e.0.7i76.0.0.input-19
net test020 <= hm2_7i76e.0.7i76.0.0.input-20

all of my test nets stay low whether or not I apply 5v to the pins. 
Do I need to change something in the FPGA firmware (bitfile?) to define these pin directions? If so, is this a matter of downloading the Xilinx tool or is there a repo somewhere with combinations of mesa bitfiles in there? I've seen PCW on here post them but I'm not sure if they live somewhere! 
Do the IOPort numbers from --readhmid directly map to the hm2_7i76e.0.7i76.0.0.input-nn pins in the hal or am I missing something here? 


When the 7i85 arrives, I'd like to get it reading a glass scale to close the loop on the axes (I could also test this sooner with the encoder input on the 7i78 if I get the scales mounted before the 7i85 shows up, depends on DHL!) presumably the standard firmware shipped in the 7i85 is set up for the right encoder IO so I only need to set up the hal file plug it into the 7i76e, or will that require an update to the 7i76e bin? 

Finally, once the axis position feedback is working and tuned I'd like to get index homing working from the glass scales on top of my existing home switches. From seeing posts on here It looks like i'll need a new bitfile to enable the home-seeking with a limit switch input and home-latch off an index, but the homing config page seems to say I just need to set HOME_USE_INDEX in the .ini ? 

A 7I76e +7I78+7i85 does need a custom bit file

For just an added 7I78 on P1, theres:

7i76e_7i76x1_7i78x1D.bit

I can make a bitfile for a 7I76E+7I78+7I85 in the next day or so

Note that if you are running LinuxCNC, and depending on the hal file setup
some I/O pins may have been enabled as outputs so it's not a great idea
to connect them to +5V.

7I76E P1 and P2 pins are pulled up so should read high if unconnected
(and not configured as outputs)

You can check this with mesaflash:

mesaflash --device ethernet --addr [card_ip_address] --rpo 0x1004
(for P1)
mesaflash --device ethernet --addr [card_ip_address] --rpo 0x1008
(for P2)

These should both read 0x001FFFF (17 bits of '1's)
with unconnected P1,P2 connectors

Legend thank you!

I stop poking around for now so and just see what mesaflash reports

Readhmid returns: 


IO Connections for on-card -> 7I76
Pin#                  I/O   Pri. func    Sec. func        Chan     Sec. Pin func   Sec. Pin Dir

TB2-4,5                  0   IOPort       StepGen          0        Dir/Table2      (Out)
TB2-2,3                    1   IOPort       StepGen          0        Step/Table1     (Out)
TB2-10,11                 2   IOPort       StepGen          1        Dir/Table2      (Out)
TB2-8,9                    3   IOPort       StepGen          1        Step/Table1     (Out)
TB2-16,17                4   IOPort       StepGen          2        Dir/Table2      (Out)
TB2-14,15                5   IOPort       StepGen          2        Step/Table1     (Out)
TB2-22,23                6   IOPort       StepGen          3        Dir/Table2      (Out)
TB2-20,21                7   IOPort       StepGen          3        Step/Table1     (Out)
TB3-4,5                    8   IOPort       StepGen          4        Dir/Table2      (Out)
TB3-2,3                    9   IOPort       StepGen          4        Step/Table1     (Out)
Internal-Field-IO      10   IOPort       SSerial          0        TXData0         (Out)
Internal-Field-IO      11   IOPort       SSerial          0        RXData0         (In)
TB3-18,19               12   IOPort       SSerial          0        TXData1         (Out)
TB3-16,17               13   IOPort       SSerial          0        RXData1         (In)
TB3-13,14              14   IOPort       QCount           0        Quad-IDX        (In)
TB3-10,11              15   IOPort       QCount           0        Quad-B          (In)
TB3-7,8                16   IOPort       QCount           0        Quad-A          (In)

IO Connections for P1
DB25 pin#             I/O   Pri. func    Sec. func        Chan     Sec. Pin func   Sec. Pin Dir

 1                      17   IOPort       StepGen         5        Dir/Table2      (Out)
14                     18   IOPort       StepGen         5        Step/Table1     (Out)
 2                      19   IOPort       StepGen         6        Dir/Table2      (Out)
15                     20   IOPort       StepGen         6        Step/Table1     (Out)
 3                      21   IOPort       StepGen         7        Dir/Table2      (Out)
16                     22   IOPort       StepGen         7        Step/Table1     (Out)
 4                      23   IOPort       StepGen         8        Dir/Table2      (Out)
17                     24   IOPort       StepGen         8        Step/Table1     (Out)
 5                      25   IOPort       PWM              0        PWM             (Out)
 6                      26   IOPort       PWM              0        /Enable         (Out)
 7                      27   IOPort       PWM              0        Dir             (Out)
 8                      28   IOPort       SSerial           0        TXData2         (Out)
 9                      29   IOPort       SSerial           0        TXEn2           (Out)
10                     30   IOPort       SSerial           0        RXData2         (In)
11                     31   IOPort       QCount           1        Quad-IDX        (In)
12                     32   IOPort       QCount           1        Quad-B          (In)
13                     33   IOPort       QCount           1        Quad-A          (In)

IO Connections for P2
DB25 pin#             I/O   Pri. func    Sec. func        Chan     Sec. Pin func   Sec. Pin Dir

 1                     34   IOPort       None
14                     35   IOPort       None
 2                     36   IOPort       None
15                     37   IOPort       None
 3                     38   IOPort       None
16                     39   IOPort       None
 4                     40   IOPort       None
17                     41   IOPort       None
 5                     42   IOPort       None
 6                     43   IOPort       None
 7                     44   IOPort       None
 8                     45   IOPort       None
 9                     46   IOPort       None
10                     47   IOPort       None
11                     48   IOPort       None
12                     49   IOPort       None
13                     50   IOPort       None


Then for the pullups I get: 
mesaflash --device ethernet --addr 10.10.10.10  --rpo 0x1005
0001FFFF

mesaflash --device ethernet --addr 10.10.10.10  --rpo 0x1004
0001FFFF
 

That looks correct (and indicates a 7I76+7I78 configuration)

all of my test nets stay low whether or not I apply 5v to the pins. 

That is expected as the input must be >60% of the field voltage to be recognized.

Here is 7i76e firmware for a 7I78 on P1 and 7I85 on P2: