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Log problems should be fixed now

Ooh that really didn't format very well I will try clean that up a little...

I've just done a clean install, installed Riocore with the installer script and I'm getting a lot of compile warnings that I have never seen before, and also it compiles in about half the time it usually takes.

It does compile, and flash but I get header wrong size errors as soon as I try to connect in LinuxCNC.

Here is the compile listing :rm -rf rio.fs rio.json rio_pnr.json rio.tcl abc.history implgw_sh rio.tcl*** GOWIN Tcl Command Line Console ***current device: GW1NR-9C GW1NR-LV9QN88PC6/I5add new file: "globals.v"add new file: "quadencoder.v"add new file: "stepdir.v"add new file: "pwmout.v"add new file: "w5500.v"add new file: "debouncer.v"add new file: "toggle.v"add new file: "pwmmod.v"add new file: "oneshot.v"add new file: "rio.v"add new file: "rio.sdc"add new file: "pins.cst"GowinSynthesis startRunning parser ...Analyzing Verilog file '/home/me/riocore/Output/TangNano9K/Gateware/globals.v'WARN (EX3209) : Root scope declaration is not allowed in Verilog 2001 mode("/home/me/riocore/Output/TangNano9K/Gateware/globals.v":1)WARN (EX3209) : Root scope declaration is not allowed in Verilog 2001 mode("/home/me/riocore/Output/TangNano9K/Gateware/globals.v":2)WARN (EX3209) : Root scope declaration is not allowed in Verilog 2001 mode("/home/me/riocore/Output/TangNano9K/Gateware/globals.v":3)WARN (EX3209) : Root scope declaration is not allowed in Verilog 2001 mode("/home/me/riocore/Output/TangNano9K/Gateware/globals.v":14)Analyzing Verilog file '/home/me/riocore/Output/TangNano9K/Gateware/quadencoder.v'Analyzing Verilog file '/home/me/riocore/Output/TangNano9K/Gateware/stepdir.v'Analyzing Verilog file '/home/me/riocore/Output/TangNano9K/Gateware/pwmout.v'Analyzing Verilog file '/home/me/riocore/Output/TangNano9K/Gateware/w5500.v'Analyzing Verilog file '/home/me/riocore/Output/TangNano9K/Gateware/debouncer.v'Analyzing Verilog file '/home/me/riocore/Output/TangNano9K/Gateware/toggle.v'Analyzing Verilog file '/home/me/riocore/Output/TangNano9K/Gateware/pwmmod.v'Analyzing Verilog file '/home/me/riocore/Output/TangNano9K/Gateware/oneshot.v'Analyzing Verilog file '/home/me/riocore/Output/TangNano9K/Gateware/rio.v'WARN (EX3073) : Port 'en' remains unconnected for this instance("/home/me/riocore/Output/TangNano9K/Gateware/rio.v":196)WARN (EX3073) : Port 'dir' remains unconnected for this instance("/home/me/riocore/Output/TangNano9K/Gateware/rio.v":205)WARN (EX3073) : Port 'rst' remains unconnected for this instance("/home/me/riocore/Output/TangNano9K/Gateware/rio.v":245)Compiling module 'rio'("/home/me/riocore/Output/TangNano9K/Gateware/rio.v":33)Compiling module 'quadencoder(QUAD_TYPE=2)'("/home/me/riocore/Output/TangNano9K/Gateware/quadencoder.v":2)Compiling module 'stepdir(PULSE_LEN=108,DIR_DELAY=18)'("/home/me/riocore/Output/TangNano9K/Gateware/stepdir.v":2)Compiling module 'pwmout(DIVIDER=2700)'("/home/me/riocore/Output/TangNano9K/Gateware/pwmout.v":2)Compiling module 'w5500(BUFFER_SIZE=16'b0000000010101000,IP_ADDR=32'b11000000101010000000101011000010,NET_MASK=32'b11111111111111111111111100000000,GW_ADDR=32'b11000000101010000000101000000001,MAC_ADDR=48'b101010101010111111111010110011001110001100011100,DIVIDER=0)'("/home/me/riocore/Output/TangNano9K/Gateware/w5500.v":3)Compiling module 'wiznet5500(IP_ADDR=32'b11000000101010000000101011000010,NET_MASK=32'b11111111111111111111111100000000,GW_ADDR=32'b11000000101010000000101000000001,MAC_ADDR=48'b101010101010111111111010110011001110001100011100,BUFFER_SIZE_RX=16'b0000000010101000,BUFFER_SIZE_TX=16'b0000000010101000,MSGID=32'b01110100011010010111001001110111)'("/home/me/riocore/Output/TangNano9K/Gateware/w5500.v":93)NOTE (EX0101) : Current top module is "rio"WARN (EX0211) : The output port "rst" of module "w5500(BUFFER_SIZE=16'b0000000010101000,IP_ADDR=32'b11000000101010000000101011000010,NET_MASK=32'b11111111111111111111111100000000,GW_ADDR=32'b11000000101010000000101000000001,MAC_ADDR=48'b101010101010111111111010110011001110001100011100,DIVIDER=0)" has no driver, assigning undriven bits to Z, simulation mismatch possible("/home/me/riocore/Output/TangNano9K/Gateware/w5500.v":21)[5%] Running netlist conversion ...Running device independent optimization ...[10%] Optimizing Phase 0 completed[15%] Optimizing Phase 1 completed[25%] Optimizing Phase 2 completedRunning inference ...[30%] Inferring Phase 0 completed[40%] Inferring Phase 1 completed[50%] Inferring Phase 2 completed[55%] Inferring Phase 3 completedRunning technical mapping ...[60%] Tech-Mapping Phase 0 completed[65%] Tech-Mapping Phase 1 completed[75%] Tech-Mapping Phase 2 completed[80%] Tech-Mapping Phase 3 completed[90%] Tech-Mapping Phase 4 completedWARN (NL0002) : The module "pwmout" instantiated to "pwmout1" is swept in optimizing("/home/me/riocore/Output/TangNano9K/Gateware/rio.v":205)[95%] Generate netlist file "/home/me/riocore/Output/TangNano9K/Gateware/impl/gwsynthesis/project.vg" completed[100%] Generate report file "/home/me/riocore/Output/TangNano9K/Gateware/impl/gwsynthesis/project_syn.rpt.html" completedGowinSynthesis finishReading netlist file: "/home/me/riocore/Output/TangNano9K/Gateware/impl/gwsynthesis/project.vg"Parsing netlist file "/home/me/riocore/Output/TangNano9K/Gateware/impl/gwsynthesis/project.vg" completedProcessing netlist completedReading constraint file: "/home/me/riocore/Output/TangNano9K/Gateware/pins.cst"Physical Constraint parsed completedRunning placement......[10%] Placement Phase 0 completed[20%] Placement Phase 1 completed[30%] Placement Phase 2 completedWARN (TA1132) : 'timestamp[0]' was determined to be a clock but was not created.[50%] Placement Phase 3 completedRunning routing......[60%] Routing Phase 0 completed[70%] Routing Phase 1 completed[80%] Routing Phase 2 completed[90%] Routing Phase 3 completedRunning timing analysis......[95%] Timing analysis completedPlacement and routing completedBitstream generation in progress......Bitstream generation completedRunning power analysis......[100%] Power analysis completedGenerate file "/home/me/riocore/Output/TangNano9K/Gateware/impl/pnr/project.power.html" completedGenerate file "/home/me/riocore/Output/TangNano9K/Gateware/impl/pnr/project.pin.html" completedGenerate file "/home/me/riocore/Output/TangNano9K/Gateware/impl/pnr/project.rpt.html" completedGenerate file "/home/me/riocore/Output/TangNano9K/Gateware/impl/pnr/project.rpt.txt" completedGenerate file "/home/me/riocore/Output/TangNano9K/Gateware/impl/pnr/project.tr.html" completedSun Jul 6 13:05:17 2025 cp -v hash_new.txt hash_compiled.txt'hash_new.txt' -> 'hash_compiled.txt'3. Resource Usage Summary 

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Resources | Usage | Utilization

---

Logic | 1084/8640 | 13%--LUT,ALU,ROM16 | 1024(721 LUT, 303 ALU, 0 ROM16) | ---SSRAM(RAM16) | 10 | -Register | 954/6693 | 15%--Logic Register as Latch | 0/6480 | 0%--Logic Register as FF | 942/6480 | 15%--I/O Register as Latch | 0/213 | 0%--I/O Register as FF | 12/213 | 6%CLS | 905/4320 | 21%I/O Port | 18/71 | 26%I/O Buf | 18 | ---Input Buf | 10 | ---Output Buf | 8 | ---Inout Buf | 0 | -================================================================================   4. I/O Bank Usage Summary 

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I/O Bank | Usage | Utilization

---

bank 1 | 10/25 | 40%bank 2 | 7/23 | 31%bank 3 | 1/23 | 5%======================================  5. Clock Resource Usage Summary 
 

Note that no axis has jog enabled, you probably need to trace these back
to halui or wherever they are supposed to come from...


29 s32 IN 38852 axis.x.jog-counts <== axis-selected-count
29 bit IN FALSE axis.x.jog-enable <== axis-select-x
29 float IN 1 axis.x.jog-scale <== selected-jog-incr
29 bit IN FALSE axis.x.jog-vel-mode
29 bit OUT FALSE axis.x.kb-jog-active
29 bit OUT FALSE axis.x.wheel-jog-active
29 float IN 1 axis.y.jog-accel-fraction
29 s32 IN 0 axis.y.jog-counts
29 bit IN FALSE axis.y.jog-enable
29 float IN 0 axis.y.jog-scale
29 bit IN FALSE axis.y.jog-vel-mode
29 bit OUT FALSE axis.y.kb-jog-active
29 bit OUT FALSE axis.y.wheel-jog-active
29 float IN 1 axis.z.jog-accel-fraction
29 s32 IN 38852 axis.z.jog-counts <== axis-selected-count
29 bit IN FALSE axis.z.jog-enable <== axis-select-z
29 float IN 1 axis.z.jog-scale <== selected-jog-incr
29 bit IN FALSE axis.z.jog-vel-mode
29 bit OUT FALSE axis.z.kb-jog-active

There is no analog input on the 7I95/7I95T so maybe an
encoder would make more sense for feed rate override.
You could use either one of the high speed encoders or
one of the 4 MPG encoders built into the isolated I/O.

Note the both MesaCT and the very latest pncconf
( in LinuxCNC master ) can make  configurations for the
7I95/7I95T.

Parrallel port has failed on my old computer , running Ubuntu 10.4 and EMC2 2.4.6 . Milling machine has Pico USC , Microkinetics Steppers , Linear Scales for Position feedback.  Old computer is a mishmash of crap that has no network capabilities.
I need the easiest upgrade path , for a computer and Software . Im old and not very tech savy!  I may go to a Mesa board if it would make things easier. Any and all recommendations!

Thanks for the "inmux" hint, it's so true that the 7i95 board has inmux-type input and output pins. Now I have connected the right input pin, and my external emergency stop button is working fine. I have added the following hal command line in my .hal file...

net estop-out iocontrol.0.user-enable-in
net external-estop-in hm2_7i95.0.inmux.00.input-00 => iocontrol.0.emc-enable-in

Let me know if it can be further simplified.

Kindly do me another favor by giving the piece of hal command line to do the x-axis feed override control using an external analog DC power supply from 0 to 10 volts 
 

How is the input wired?

The 7I95/7I95T input pairs have an input common
so if you are supplying +5V to the input, the input common
must connect to 5V common (negative)

Note the you have to have 5V to reliably activate the input
4V is marginal (the input threshold is about 3.9V)

Make sure you are using the "WATCH" tab in halshow
not "SHOW"

Also note that  the 7I95/7I95T isolated inputs are not hal GPIO
pins but rather hal Inmux pins (0..23). 
 

Thank you for the quick reply. 

I am trying to use input pin 0 on the TB6 tab of the Mesa 7i95 board. I am supplying 5 volts on and off, but the status of the input pin (hm2_7i95.0.gpio.000.in) is not changing in the Halshow monitor window, but the LED of the mesa board of the 0 input pin is getting on and off.
[img]blob:https://web.whatsapp.com/4e39dfa6-8d10-42c3-af3d-452f787f1698[/img]

I want to add an emergency stop and feed override button.

I have asked the same question ("Adding external switch for emergency stop and feed override") in my thread posted one day before, requesting you to look at that also if possible.

www.mesanet.com/software/parallel/7i92t.zip

I tried using the source and did find an issue, there's a WIP
source file that needs to be deleted from the project:

qcountersfpdsi.vhd  (quadrature counter with simulated index)

I will fix the downloadable source on Monday


 

Which inputs pins? 

The isolated inputs TB6 + TB5 pins 1..12 will accept from 5 to 36V

I have a similar problem, and the input pins of the Mesa 7i95 are randomly active. I have supplied a voltage of 24 volts to these pins mistakenly. I have to use some input output functionality in real-time. what is another way to use some input output?

1. measure the voltage powering the drives at standstill, when 1 axis is moving and when both axis are moving.
2. while motors are enabled and not turning, use pliers and try to move the motor, how much does it roughly move?

I have not. forgot. 25 days of work in a row can do that

I would love the vertical fixes.

Also opinion - should vert have a sim folder for it's self?
It's kinda hidden I suppose

What are the chances of this being a slow SD card issue?
It sure points that way...