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On Xilinx you can edit the .ucf file and add the "PULLDOWN" constraint 
but the I/O pins will float during powerup/configuration.

For 50 pin cards, it's much easier to just reverse the pullup resistors
and the GPIO will be guaranteed to be low at all times (and with a known
pulldown resistance)
 

low-blip wrote:

Did you figure it out? I want to use a Rust library in my VCP, but I only know how to install it as a package in a virtual environment.
 

Oh gosh, I can't remember! It's been so long since I worked on that project! I’m definitely using a venv, but I'm not sure I was able to switch the Python interpreter.

I was looking at upgrading my J1900 brix to a brix with an i7-5775 and 16gr of ram. Is this a fool’s errand or will this help future proof my system?

ps I snagged a BRIX with a i7-5775 for a killer deal so it’s on its way. 

What do you mean after configuration?
After loading firmware from flash memory?
When you powering fpga the firmware loads almost immediately...
How to enable xilinx weak internal pulldowns?