In TopGCSPIHostMot2.vhd did you change the clock setups to match the crystal you are using ?
When the hm2_rpspi driver is loading it is not getting the correct cookie.
This is the section you need to change
Code:
ClockMultH : DCM
generic map (
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 2,
CLKFX_MULTIPLY => 8, -- 8 FOR 200 MHz
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => X"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (
CLK0 => clk0_0, --
CLKFB => clk0_0, -- DCM clock feedback
CLKFX => clkfx0,
CLKIN => CLK, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
BUFG_inst0 : BUFG
port map (
O => fclk, -- Clock buffer output
I => clkfx0 -- Clock buffer input
);
ClockMultM : DCM
generic map (
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 2,
CLKFX_MULTIPLY => 4, -- 4 FOR 100 MHz
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => X"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (
CLK0 => clk0_1, --
CLKFB => clk0_1, -- DCM clock feedback
CLKFX => clkfx1,
CLKIN => CLK, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
BUFG_inst1 : BUFG
port map (
O => clklow, -- Clock buffer output
I => clkfx1 -- Clock buffer input
);
-- End of DCM_inst instantiation
For a 50Mhz clock (std on Mesa boards) the base clock is initially divided by 2 and the multiplied by the following to get the desired frequencies. As you seem to e using a 12MHz clock I'm not too sure the actual values you will need, hopefully PCW will have the answers.
CLKFX_MULTIPLY => 8, -- 8 FOR 200 MHz
CLKFX_MULTIPLY => 4, -- 4 FOR 100 MHz
When using a 100Mhz clock
CLKFX_MULTIPLY => 4, -- 4 FOR 200 MHz
CLKFX_MULTIPLY => 2, -- 2 FOR 100 MHz
And when using a 25MHz clock
CLKFX_MULTIPLY => 16, -- 16 FOR 200 MHz
CLKFX_MULTIPLY => 8, -- 8 FOR 100 MHz
