5I25 custom Pinout
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21 Sep 2013 23:01 - 21 Sep 2013 23:02 #39078
by rene-dev
5I25 custom Pinout was created by rene-dev
Hi,
I am using a 5I25 with a custom breakout board.
Currently I am using the PIN_R990x2_34 bitfile, as it is very close to my configuration.
Now I need more encoders, and based on the r990 pinfile I created the attached pinfile,
and built the bitfile using the current ISE version.
mesaflash --verify confirmed the bitfile was flashed.
the stepgens are still working.
However, the hostmot hal module fails to see the additional encoder:
Is there any documentation on creating pinfiles?
Does the hal module need to know about the additional encoder?
Thanks,
Rene
I am using a 5I25 with a custom breakout board.
Currently I am using the PIN_R990x2_34 bitfile, as it is very close to my configuration.
Now I need more encoders, and based on the r990 pinfile I created the attached pinfile,
and built the bitfile using the current ISE version.
mesaflash --verify confirmed the bitfile was flashed.
the stepgens are still working.
However, the hostmot hal module fails to see the additional encoder:
[ 757.086111] hm2: loading Mesa HostMot2 driver version 0.15
[ 757.092833] hm2_pci: loading Mesa AnyIO HostMot2 driver version 0.7
[ 757.092890] hm2_pci 0000:05:00.0: PCI INT A -> GSI 20 (level, low) -> IRQ 20
[ 757.092898] hm2_pci: discovered 5i25 at 0000:05:00.0
[ 757.093128] hm2/hm2_5i25.0: config.num_encoders=3, but only 2 are available, not loading driver
[ 757.093137] hm2/hm2_5i25.0: failed to parse Module Descriptor 2
[ 757.093148] hm2_5i25.0: board fails HM2 registration
[ 757.093165] hm2_pci 0000:05:00.0: PCI INT A disabled
[ 757.093179] hm2_pci: probe of 0000:05:00.0 failed with error -22
[ 757.664629] hm2: unloadingIs there any documentation on creating pinfiles?
Does the hal module need to know about the additional encoder?
Thanks,
Rene
Last edit: 21 Sep 2013 23:02 by rene-dev. Reason: attached file
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22 Sep 2013 00:06 #39080
by PCW
Replied by PCW on topic 5I25 custom Pinout
Can you rename your new pin_xxxx.vhd file to pin_xxxx.txt
and post it here?
(The forum is picky about attachments but will accept .zip and .txt files)
and post it here?
(The forum is picky about attachments but will accept .zip and .txt files)
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22 Sep 2013 02:44 #39086
by rene-dev
Replied by rene-dev on topic 5I25 custom Pinout
this is based on guessing and reading on this forum.
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22 Sep 2013 02:45 #39087
by rene-dev
Replied by rene-dev on topic 5I25 custom Pinout
It does not seem to like my file.
library IEEE;
use IEEE.std_logic_1164.all; -- defines std_logic types
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
use work.IDROMConst.all;
package PIN_KNUTH is
constant ModuleID : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"03", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(StepGenTag, x"02", ClockLowTag, x"04", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(PWMTag, x"00", ClockHighTag, x"02", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc : PinDescType :=(
-- Base func sec unit sec func sec pin -- external DB25
IOPortTag & x"00" & NullTag & NullPin, -- I/O 00 PIN 1 Spindel CCW
IOPortTag & x"00" & NullTag & NullPin, -- I/O 01 PIN 14 Spindel CW
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 02 PIN 2 X Dir
IOPortTag & x"00" & NullTag & NullPin, -- I/O 03 PIN 15 ref A
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 04 PIN 3 X Step
IOPortTag & x"00" & NullTag & NullPin, -- I/O 05 PIN 16 watchdog
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 06 PIN 4 Y Dir
IOPortTag & x"00" & NullTag & NullPin, -- I/O 07 PIN 17 nix
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 08 PIN 5 Y Step
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 09 PIN 6 Z Dir
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 10 PIN 7 Z Step
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 11 PIN 8 A Dir
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 12 PIN 9 A Step
IOPortTag & x"00" & NullTag & NullPin, -- I/O 13 PIN 10 ref Z
IOPortTag & x"00" & NullTag & NullPin, -- I/O 14 PIN 11 estop in
IOPortTag & x"00" & NullTag & NullPin, -- I/O 15 PIN 12 ref Y
IOPortTag & x"00" & NullTag & NullPin, -- I/O 16 PIN 13 ref X
-- 26 HDR -- IDC DB25
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 17 PIN 1 Input 1 (Quad A)
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 18 PIN 2 Input 1 (Quad B)
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 19 PIN 3 Input 2 (Quad A)
IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 20 PIN 4 Input 2 (Quad B)
IOPortTag & x"02" & QCountTag & QCountQAPin, -- I/O 21 PIN 5 Input 3 (Quad A)
IOPortTag & x"02" & QCountTag & QCountQBPin, -- I/O 22 PIN 6 Input 3 (Quad B)
IOPortTag & x"00" & NullTag & NullPin, -- I/O 23 PIN 7 just GPIO
IOPortTag & x"00" & NullTag & NullPin, -- I/O 24 PIN 8 just GPIO
IOPortTag & x"00" & NullTag & NullPin, -- I/O 25 PIN 9 just GPIO
IOPortTag & x"00" & NullTag & NullPin, -- I/O 26 PIN 11 just GPIO
IOPortTag & x"00" & NullTag & NullPin, -- I/O 27 PIN 13 just GPIO
IOPortTag & x"00" & NullTag & NullPin, -- I/O 28 PIN 15 just GPIO
IOPortTag & x"00" & NullTag & NullPin, -- I/O 29 PIN 17 just GPIO
IOPortTag & x"06" & NullTag & NullPin, -- I/O 30 PIN 19 just GPIO
IOPortTag & x"00" & NullTag & NullPin, -- I/O 31 PIN 21 just GPIO
IOPortTag & x"00" & NullTag & NullPin, -- I/O 32 PIN 23 just GPIO
IOPortTag & x"00" & NullTag & NullPin, -- I/O 33 PIN 25 just GPIO
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for 34 pin 5I25
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
end package PIN_KNUTH;Please Log in or Create an account to join the conversation.
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22 Sep 2013 03:17 #39088
by PCW
Replied by PCW on topic 5I25 custom Pinout
It looks about right
Did you cycle the PC power to load the new configuration?
Did you cycle the PC power to load the new configuration?
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22 Sep 2013 03:24 #39090
by rene-dev
Replied by rene-dev on topic 5I25 custom Pinout
I did powercycle.
Does it matter when I have modules in ModuleID that are not mapped to any IO? like the PWM.
I reduced the number of stepgens, and I can have up to 8, which should not be possible with the new configuration.
But mesaflash --verify confirms that the new bitfile is flashed.
Rene
Does it matter when I have modules in ModuleID that are not mapped to any IO? like the PWM.
I reduced the number of stepgens, and I can have up to 8, which should not be possible with the new configuration.
But mesaflash --verify confirms that the new bitfile is flashed.
Rene
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22 Sep 2013 03:52 - 22 Sep 2013 03:54 #39091
by PCW
Replied by PCW on topic 5I25 custom Pinout
It should not matter if you have unused modules (actually there are several modules that have no I/O pins) though for the PWM gen I would remove it since its just wasting space.
You can have as many stepgens as will fit, some parts of the stepgen will be optimized away if the output pins are not there, but since the stepgen position register is readable, the stepgen will still be created.
Note that mesaflash reads back the SPI flash chip on the card, not the FPGA configuration, you still have to power cycle (_NOT_ reset/reboot) the computer to load the newly flashed configuration in the SPI flash to the FPGA
You can have as many stepgens as will fit, some parts of the stepgen will be optimized away if the output pins are not there, but since the stepgen position register is readable, the stepgen will still be created.
Note that mesaflash reads back the SPI flash chip on the card, not the FPGA configuration, you still have to power cycle (_NOT_ reset/reboot) the computer to load the newly flashed configuration in the SPI flash to the FPGA
Last edit: 22 Sep 2013 03:54 by PCW. Reason: sp
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22 Sep 2013 03:57 #39092
by rene-dev
Replied by rene-dev on topic 5I25 custom Pinout
I just rebooted, thought that would turn off the PCI power supply rail.
I am back in my workshop tomorrow and will try it again with proper powercycle(as in pulling the plug).
Thanks!
I am back in my workshop tomorrow and will try it again with proper powercycle(as in pulling the plug).
Thanks!
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22 Sep 2013 04:19 #39095
by PCW
Replied by PCW on topic 5I25 custom Pinout
A reboot will cause a PCI reset but does not affect the power
The default 5I25 jumpering requires a power cycle to reload the FPGA configuration
The default 5I25 jumpering requires a power cycle to reload the FPGA configuration
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23 Sep 2013 02:08 #39112
by rene-dev
Replied by rene-dev on topic 5I25 custom Pinout
yes, that worked. Thanks again.
Would it be possible to connect PCI reset to the FPGA reset?(just a stupid idea)
Just a couple of questions:
What are the "emptypin"s for, and how many are needed?
do they fill PinDescType up to a hardcoded limit?
Are there still addresses available for additional modules, or do I need to replace some when I create a custom module?
is there a hardcoded limit of 32 modules? because there are 32 NullTag modules.
What I need are a lot more I/Os, I was thinking a I2C/shift register/modbus port expander, which is transparent to the hal module.
I would like a portexpander in each switching cabinet of the mill.
The expanders do not need to be high speed for encoders or stepgens.
Rene
Would it be possible to connect PCI reset to the FPGA reset?(just a stupid idea)
Just a couple of questions:
What are the "emptypin"s for, and how many are needed?
do they fill PinDescType up to a hardcoded limit?
Are there still addresses available for additional modules, or do I need to replace some when I create a custom module?
is there a hardcoded limit of 32 modules? because there are 32 NullTag modules.
What I need are a lot more I/Os, I was thinking a I2C/shift register/modbus port expander, which is transparent to the hal module.
I would like a portexpander in each switching cabinet of the mill.
The expanders do not need to be high speed for encoders or stepgens.
Rene
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