5I25 custom Pinout
23 Sep 2013 04:37 - 23 Sep 2013 04:46 #39115
by PCW
Replied by PCW on topic 5I25 custom Pinout
The 5I25 is deliberately reconfigured only on power up as its the most conservative option. There is a solder jumper to force re-configuration on PCI reset but the default assembly uses Power On Reset (POR)
The empty pins are because you are actually building a constant array to be loaded into the IDROM (256X32 ROM that tells the driver what modules are included, what their base addresses are, their pinout requirements etc, etc)
The address space is nearly full but there is no actual reason not to re-use addresses used by other modules (in fact the addresses could be assigned dynamically at VHDL compile time with more clever hostmot2 source)
There is a hardcoded limit of 32 module types per configuration (though I dont think any configs have more than 9 or so modules) GTAGs are 8 bits which means there's a hard coded limit of 256 module types
There is a framework for I/O expansion (sserial) which allows transparent/self discovered I/O expansion beyond 1500 I/O points. Sserial uses full duplex serial links at 2.5M baud. The remote I/O device is usually a ucontroller or a FPGA, that is
something with enough intelligence/storage to implement the communication protocol
and provide the discovery dictionary that specifies the hal names, data types,directions,scaling etc etc.
The empty pins are because you are actually building a constant array to be loaded into the IDROM (256X32 ROM that tells the driver what modules are included, what their base addresses are, their pinout requirements etc, etc)
The address space is nearly full but there is no actual reason not to re-use addresses used by other modules (in fact the addresses could be assigned dynamically at VHDL compile time with more clever hostmot2 source)
There is a hardcoded limit of 32 module types per configuration (though I dont think any configs have more than 9 or so modules) GTAGs are 8 bits which means there's a hard coded limit of 256 module types
There is a framework for I/O expansion (sserial) which allows transparent/self discovered I/O expansion beyond 1500 I/O points. Sserial uses full duplex serial links at 2.5M baud. The remote I/O device is usually a ucontroller or a FPGA, that is
something with enough intelligence/storage to implement the communication protocol
and provide the discovery dictionary that specifies the hal names, data types,directions,scaling etc etc.
Last edit: 23 Sep 2013 04:46 by PCW. Reason: sp
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23 Sep 2013 05:04 #39118
by rene-dev
Replied by rene-dev on topic 5I25 custom Pinout
The POR solder jumper does not seem to be documented.
So the IDROM does not, but could in the future, contain the register map?
Is there any source available for sserial expanders?
Or any further Documentation about the SPI commands it uses, other than the VHDL code?
Rene
So the IDROM does not, but could in the future, contain the register map?
Is there any source available for sserial expanders?
Or any further Documentation about the SPI commands it uses, other than the VHDL code?
Rene
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23 Sep 2013 07:16 #39120
by PCW
Replied by PCW on topic 5I25 custom Pinout
Actually the IDROM does contain the most of the regmap information (other than the individual register descriptions as that is too much information for small FPGAs)
Sserial does not use SPI but rather asynchronous serial as this is easier to send long distances, isolate (only 2 pins, no clock skew issues), and allows use of an inexpensive ucontroller as the remote I/O expansion device.
The sserial protocol and discovery scheme are all documented in any of our sserial remote manuals (7i76man.pdf for example)
Sserial does not use SPI but rather asynchronous serial as this is easier to send long distances, isolate (only 2 pins, no clock skew issues), and allows use of an inexpensive ucontroller as the remote I/O expansion device.
The sserial protocol and discovery scheme are all documented in any of our sserial remote manuals (7i76man.pdf for example)
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