Fanuc ABS encoder data transmission not complete

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21 Oct 2021 20:05 #223834 by ArkaumIndustries
I configured a 5i24 to use the fanuc abs module and dont have a dpll. Whenever i start linuxCNC, after a few seconds i get an error saying "data transmission not complete" and "you may need to change the timing of the trigger function". I scoped the TX pin and only get a ~1.6us request pulse when the encoder need ~7.8us. How can I change the length of the request pulse?

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21 Oct 2021 21:38 #223837 by andypugh
From the regmap (part of the hostmot2.zip file)
**************************************************
Fanuc absolute encoder interface. Interfaces to Fanuc serial absolute encoders

DataReg0

0x1500 32 bit serial data 0..31 for FAbs channel 0
0x1504 32 bit serial data 0..31 for FAbs channel 1
0x1508 32 bit serial data 0..31 for FAbs channel 2

Writing to DataReg0 starts a transfer request on the selected
FanucAbs module

...
DataReg1

0x1600 32 bit serial data 32..63 for FAbs channel 0
0x1604 32 bit serial data 32..63 for FAbs channel 1
0x1608 32 bit serial data 32..63 for FAbs channel 2
...
DataReg2

0x1700 12 bit serial data 64..75 for FAbs channel 0 (right justified)
0x1704 12 bit serial data 64..75 for FAbs channel 1 (right justified)
0x1708 12 bit serial data 64..75 for FAbs channel 2 (right justified)
...
DataReg 2 is also used for optional setup bits and a cable error status bit
Bit 31	CableErr     (R/O) If this bit is set, it indicates that the data 
                     polarity is wrong or the cable is unplugged
Bits 24..30	     Bit Length ((default 76) only writeable 
     		     if write setup enable bit is set
Bit 14..23	     Request length register, default 8 Usec. only writeable
    		     if write setup enable bit is set

Request length is request length register value * clocklow period


Data
Note: Fanuc serial encoder data is LSb first so is right shifted, 
and ends up left justified in the three data registers

0x1800 Control register 0 for FAbs channel 0
0x1804 Control register 0 for FAbs channel 1
0x1808 Control register 0 for FAbs channel 2
...

Control register 0 fields:

Bit 15		 Data Available set by transfer done, cleared by reading data 0 register
Bit 12..14	 Timer channel select
Bit 11		 Busy bit, set when transfer is started, 
   		 cleared when all data bits are recieved 
Bit 10		 RXGo set when recieve data start bit is detected
    		 cleared when all data bits are received     
Bit 9		 TStartMask, if set, timer start transfer is allowed
Bit 8		 GstartMask, if set global start transfer is allowed
Bit 7		 Setup Write Enable register


The timer select register selects the desired timer output
from the DPLL timer module: 0=Ref 1=timer1, 2=timer2, 3=timer3, 4=timer4
The TStartMask must be set to enable timer starts. 

0x1900 Control register 1 for FAbs channel 0
0x1904 Control register 1 for FAbs channel 1
0x1908 Control register 1 for FAbs channel 2
...

Control register 1
Bits 0..19	 Bitrate select register. (default set for 1.024 MHz bit rate)
     		 Only writeable if write setup enable bit is set
Bits 28..31	 Digital filter setting in clock low counts (default  0xF)
    		 Only writeble if write setup enable bit is set

Note a digital filter value of 0 will not work (only 1..15 are valid)

Receive bitrate is generated by a 20 bit phase accumulator. 
Bitrate is: (Control_Register_1/1048576)*ClockLow
re-arranged this is Control_Register_1 = 1048576*Bitrate/ClockLow

0x1A00 Global start register/busy register. Writing the global start register
(data is dont-care) starts transfers on all FanucAbs modules that have their 
global start mask set. 

Reading the Global start register returns the busy status of each channel, 
with bit# = channel# A channel is busy if the transfer is in progress or 
the data is stale (its already been read)  

Fanuc data format (76 bits): So far just for Aa64 (860-360-xxx)
bits 0..4 	constant : encoder type?
bit  5     	1=battery fail
bits 6,7	unknown
bit  8		1=un-indexed
bits 9..17	unknown, perhaps for higher res encoders
bits 18..33	16 bit absolute encoder data (0..65535 for one turn)
bits 34..35      unknown
bits 36..51	16 bit absolute turns count
bits 52,53	unknown
bits 54..63	10 bit absolute commutation encoder (four 0.1023 cycles per turn)
bits 64..70	unknown
bits 71..75	ITU CRC-5 (calculated MSB first)

These encoders are absolute if the battery backup is maintained since the 
last homing. This can be determined by the status of the un-indexed bit, 
at least until the encoder crosses index. Surprisingly 
(well it surprised me anyway) the encoders maintain position with battery 
power alone. It appears that they keep the LEDS/processor alive with a 
few uA of battery power (probably low duty cycle LED pulsing/analog circuits 
power cycling). This can be verified by reading the battery current and then 
moving the encoder, it goes from a few uA to many mA with a slow encoder move.

The commutation track is always absolute so can be used for commutation 
data regardless of the index status. Note that the commutation track
seems to be interpolated so is not better than maybe 1% accuracy
 
Note that the timing/baudrate are all precalculated so should not need
changing, but can be changed by setting the setup enable bit in control reg 0

It _should_ be 8┬Ás according to that.

You should be able to modify that register in "raw mode"
linuxcnc.org/docs/2.8/html/man/man9/hostmot2.9.html#Raw%20Mode

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21 Oct 2021 22:44 #223847 by PCW
Also does any absolute encoder work without the DPLL?
I would think that would be problematic

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21 Oct 2021 23:13 #223852 by ArkaumIndustries
I can try adding the DPLL, from what I gather its not necessarily required, but I will try to get it added.
I tried using raw mode to view the registers but I wasn't able to get it to make anymore hal pins available. All that I need to change is adding "enable_raw" to the hm2_pci config correct?

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21 Oct 2021 23:50 #223855 by ArkaumIndustries
I added the the DPLL to the fpga firmware, I'm assuming there is some configuration that needs done on the hal side to get it set up correctly. Are there any examples of a hal config for fanuc encoders?

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22 Oct 2021 00:05 #223857 by tommylight
The following user(s) said Thank You: ArkaumIndustries

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22 Oct 2021 01:57 #223867 by ArkaumIndustries
I looked at your hal files and mine appear to be not far off. Do you have any information on the fpga clock frequencies? Currently mine is 33.33Mhz low and 200Mhz high.

I still cannot get enable_raw to work, id like to check the register that determines the request pulse length, but I cant get access to any of the raw pins.

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22 Oct 2021 19:58 #223950 by ArkaumIndustries
I was able to fix the issues, the dpll wasn't set up correctly, but now the request signal is good.

However there is an issue with reading the bit stream back from the encoder, there are 9 high bits at the beginning of every transmission from the encoder, but hostmot2 is expecting to get directly into data, this shifts all the bits and gives bad readings. Is there a way to have it ignore the first few bits. I thought about using SSI instead but it only supports 64 bits and not the 76 that fanuc encoders use. It is also an A64 encoder so I'm not sure why the bit stream is different.

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22 Oct 2021 20:01 - 22 Oct 2021 20:15 #223952 by PCW
is possible you have data or request polarity incorrect?
Last edit: 22 Oct 2021 20:15 by PCW.

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22 Oct 2021 20:03 #223953 by ArkaumIndustries
I tried flipping the data wires and it didn't fix the issue

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