LinuxCNC-RIO - RealtimeIO for LinuxCNC based on FPGA (ICE40 / ECP5)

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1 year 4 months ago #330333 by meister
I'm afraid there is still a bug when generating the ini/hal.

scale in need to be set in the encoder config (signals -> scale):


and out in the joint pwm/dir config (joint -> General -> Scale):

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1 year 4 months ago #330335 by epineh

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1 year 4 months ago #330476 by DMNZ
I've been looking into RIO for couple of days, reading forums and one question i can't find the answer for, may be it is obvious for all but me, what is the data protocol used in RIO over the spi? is it the same as Mesa LBP16 commands requiring hostmot2 or something else?

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1 year 4 months ago #330495 by meister
there is no real protocol,
it is a frame with a fixed length (depending on the config) in which all necessary data is sent and received in byte blocks.

Here is an example of the default Tangbob config:
Code:
cat Output/Tangbob/DOC/INTERFACE.md # Interface ## Host to FPGA | POS | SIZE | NAME | | --- | --- | --- | | 0 | 32bits | RX_HEADER | | 32 | 128bits | VAROUT128_MODBUS0_TXDATA | | 160 | 32bits | VAROUT32_PWMOUT0_DTY | | 192 | 32bits | VAROUT32_STEPDIR0_VELOCITY | | 224 | 32bits | VAROUT32_STEPDIR1_VELOCITY | | 256 | 32bits | VAROUT32_STEPDIR2_VELOCITY | | 288 | 32bits | VAROUT32_STEPDIR3_VELOCITY | | 320 | 1bit | VAROUT1_WLED0_0_GREEN | | 321 | 1bit | VAROUT1_WLED0_0_BLUE | | 322 | 1bit | VAROUT1_WLED0_0_RED | | 323 | 1bit | VAROUT1_BITOUT0_BIT | | 324 | 1bit | VAROUT1_BITOUT1_BIT | | 325 | 1bit | VAROUT1_PWMOUT0_ENABLE | | 326 | 1bit | VAROUT1_STEPDIR0_ENABLE | | 327 | 1bit | VAROUT1_STEPDIR1_ENABLE | | 328 | 1bit | VAROUT1_STEPDIR2_ENABLE | | 329 | 1bit | VAROUT1_STEPDIR3_ENABLE | ## FPGA to Host | POS | SIZE | NAME | | --- | --- | --- | | 0 | 32bits | TX_HEADER | | 32 | 32bits | TIMESTAMP | | 64 | 16bits | MULTIPLEXED_INPUT_VALUE | | 80 | 8bits | MULTIPLEXED_INPUT_ID | | 88 | 128bits | VARIN128_MODBUS0_RXDATA | | 216 | 32bits | VARIN32_STEPDIR0_POSITION | | 248 | 32bits | VARIN32_STEPDIR1_POSITION | | 280 | 32bits | VARIN32_STEPDIR2_POSITION | | 312 | 32bits | VARIN32_STEPDIR3_POSITION | | 344 | 1bit | VARIN1_BITIN0_BIT | | 345 | 1bit | VARIN1_BITIN1_BIT | | 346 | 1bit | VARIN1_BITIN2_BIT | | 347 | 1bit | VARIN1_BITIN3_BIT | | 348 | 1bit | VARIN1_BITIN4_BIT |

the frames are then filled with zeros so that they are always divisible by 8 bits and RX and TX frames have the same length so that they can be transmitted via SPI full duplex

a hal component (riocomp.c) is also generated for each config, which can read and write the frames and, if necessary, does a few floating point calculations that I wanted to keep away from the FPGA

This makes it possible to manage without SoftCore in the FPGA, i.e. only pure logic


 

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1 year 4 months ago #330497 by DMNZ
wow, great answer thank you. i was close in my thoughts, since there is no cpu and in rio.c you compile riocomp i thought that there must be something like fixed data frame structure adjusted for each config, but you made it very clear.
do you do anything about noise? like CRC (checksum) maybe for each frame in case it gets corrupted?

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1 year 4 months ago #330523 by meister
no checksum for SPI, it's only for short distance. only the UDP and RS485/RS422 connections have checksum

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