3pwmgen
25 Jul 2015 01:03 #60892
by andypugh
What output do you actually want? What are you driving? Do you want a PWM signal or three analogue voltages?
If you need three + / - 10V signals in a 120-degrees phase relationship then the bldc HAL component and a standard SV..... + 7i33 configuration should work.
What makes the Mesa firmware 3pwmgen distinct is that the three PWM outputs are phase-locked and can drive H-bridges directly.
So if we have lathe with 2 axis and spindle driven by 3pwm we can not just use 3 7i33 to take 9 of their pwms as 3 3pwmgens?
What output do you actually want? What are you driving? Do you want a PWM signal or three analogue voltages?
If you need three + / - 10V signals in a 120-degrees phase relationship then the bldc HAL component and a standard SV..... + 7i33 configuration should work.
What makes the Mesa firmware 3pwmgen distinct is that the three PWM outputs are phase-locked and can drive H-bridges directly.
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27 Jul 2015 19:38 #60956
by andypugh
It looks like it needs all 6 PWM channels, so this does look like 3-phase PWM output is required.
Do you have any idea what the control voltage is? It might be logic level (in which case the 7i42 would be right) or it might require gate-drivers, in which case you would need PCW to advise.
What boards can be used to connect 5i20 to this amplifier?
7i42, 7i37?
It looks like it needs all 6 PWM channels, so this does look like 3-phase PWM output is required.
Do you have any idea what the control voltage is? It might be logic level (in which case the 7i42 would be right) or it might require gate-drivers, in which case you would need PCW to advise.
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27 Jul 2015 20:51 #60960
by PCW
Ahh Fanuc...
Those drives use 4 or 8 KHz 3 phase PWM, but there are some tricks
1. Drive status is read from the PWM signals when the drive is not ready (*DRDY is high) so pin direction needs to change
with *DRDY
2. 2 phase current feedback is provided in analog form ~(+-4V) on IS and IR (third phase current is difference)
3. This means that the current loop must be run in the controller = speed required
4. I have considered making a multi channel daughterboard for Fanuc drives of this type (and the newer ones that use the high density connector instead of the Honda connector the 6058 uses) but simply dont have enough time
Those drives use 4 or 8 KHz 3 phase PWM, but there are some tricks
1. Drive status is read from the PWM signals when the drive is not ready (*DRDY is high) so pin direction needs to change
with *DRDY
2. 2 phase current feedback is provided in analog form ~(+-4V) on IS and IR (third phase current is difference)
3. This means that the current loop must be run in the controller = speed required
4. I have considered making a multi channel daughterboard for Fanuc drives of this type (and the newer ones that use the high density connector instead of the Honda connector the 6058 uses) but simply dont have enough time
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28 Jul 2015 14:57 #60979
by Nick
Will it be still needed if we have encoder on the motor's shaft?
Or are they so important?
2. 2 phase current feedback is provided in analog form ~(+-4V) on IS and IR (third phase current is difference)
3. This means that the current loop must be run in the controller = speed required
Will it be still needed if we have encoder on the motor's shaft?
Can we use manual switch to sekect read/write mode for this signals?1. Drive status is read from the PWM signals when the drive is not ready (*DRDY is high) so pin direction needs to change
with *DRDY
Or are they so important?
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29 Jul 2015 22:07 #61016
by PCW
You may get away without reading the status pins AFAICR the status outputs are open drain
that is the PWM pins are pulled up at the 6058 and the status outputs pull down selected pins
so you might be able to read them by:
1. Using a bi-directional interface like a 7I42
2. Using open drain output mode on the PWM pins
3. Invert the PWM pins polarity (using invert_output attribute)
4. When *DRDY is high (not ready) disable PWM outputs
(this will make the PWM outputs high = float when in open drain mode)
5. now you can read the status bits on the PWM pins
Note this may require adding stiffer pullups to the FPGA outputs, not sure how stiff the pullups are on the 6058
The issue with not having a current feedback loop is that you are running the motor in voltage mode
and it will be very easy to overcurrent the motor (not sure what overcurrent protections are built in to the drive)
that is the PWM pins are pulled up at the 6058 and the status outputs pull down selected pins
so you might be able to read them by:
1. Using a bi-directional interface like a 7I42
2. Using open drain output mode on the PWM pins
3. Invert the PWM pins polarity (using invert_output attribute)
4. When *DRDY is high (not ready) disable PWM outputs
(this will make the PWM outputs high = float when in open drain mode)
5. now you can read the status bits on the PWM pins
Note this may require adding stiffer pullups to the FPGA outputs, not sure how stiff the pullups are on the 6058
The issue with not having a current feedback loop is that you are running the motor in voltage mode
and it will be very easy to overcurrent the motor (not sure what overcurrent protections are built in to the drive)
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