Spinx1 to 7i85
07 Nov 2015 07:03 #64935
by OT-CNC
Replied by OT-CNC on topic Spinx1 to 7i85
Hi PCW,
I'm sorry to be a pain about this. Any updates on the firmware progress?
Thanks again for your time, your help is much appreciated.
I'm sorry to be a pain about this. Any updates on the firmware progress?
Thanks again for your time, your help is much appreciated.
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07 Nov 2015 12:23 #64947
by PCW
Replied by PCW on topic Spinx1 to 7i85
freeby.mesanet.com/5i25_7i85sspx2.bit
has the 4th stepgen replaced with PWM and DIR
has the 4th stepgen replaced with PWM and DIR
The following user(s) said Thank You: OT-CNC
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09 Nov 2015 15:18 #65014
by OT-CNC
Replied by OT-CNC on topic Spinx1 to 7i85
Thank you PCW 
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09 Nov 2015 15:46 #65016
by OT-CNC
Replied by OT-CNC on topic Spinx1 to 7i85
I updated the firmware and ran dmesg.
If I understand correctly, the PWM is found on differential output 6 and 7 on my 5i85. I read the hostmot2 driver documentation but need some further guidance on how to connect the signals properly. What is next?
What pwm frequency can I use with the 5i25 and spin x? What setting to get direction signal from pwm pin? How to implement the pwm enable in hostmot2?
Is there an output available to wire the spinx enable pin?
Ideally I need the configuration parts to copy into my hal and ini to get this working. Do you have a sample config I can work with?
Thank you!
If I understand correctly, the PWM is found on differential output 6 and 7 on my 5i85. I read the hostmot2 driver documentation but need some further guidance on how to connect the signals properly. What is next?
What pwm frequency can I use with the 5i25 and spin x? What setting to get direction signal from pwm pin? How to implement the pwm enable in hostmot2?
Is there an output available to wire the spinx enable pin?
Ideally I need the configuration parts to copy into my hal and ini to get this working. Do you have a sample config I can work with?
Thank you!
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09 Nov 2015 16:11 #65022
by andypugh
Can you do the following to get a HAL pin list, then I can write a HAL section without guesswork.
open a terminal and type
Then copy and paste the whole output of the terminal session into a text file and attach it to a post here.
Replied by andypugh on topic Spinx1 to 7i85
Ideally I need the configuration parts to copy into my hal and ini to get this working. Do you have a sample config I can work with?
Can you do the following to get a HAL pin list, then I can write a HAL section without guesswork.
open a terminal and type
halrun
loadrt hostmot2
loadrt hm2_pci
show pin
show paramThen copy and paste the whole output of the terminal session into a text file and attach it to a post here.
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10 Nov 2015 01:43 #65054
by OT-CNC
Replied by OT-CNC on topic Spinx1 to 7i85
Sweet, here is the output of the terminal session:
5 float OUT 0 hm2_5i25.0.encoder.02.position
5 float OUT 0 hm2_5i25.0.encoder.02.position-latched
5 bit OUT FALSE hm2_5i25.0.encoder.02.quad-error
5 bit IN FALSE hm2_5i25.0.encoder.02.quad-error-enable
5 s32 OUT 0 hm2_5i25.0.encoder.02.rawcounts
5 s32 OUT 0 hm2_5i25.0.encoder.02.rawlatch
5 bit IN FALSE hm2_5i25.0.encoder.02.reset
5 float OUT 0 hm2_5i25.0.encoder.02.velocity
5 s32 OUT 0 hm2_5i25.0.encoder.03.count
5 s32 OUT 0 hm2_5i25.0.encoder.03.count-latched
5 bit I/O FALSE hm2_5i25.0.encoder.03.index-enable
5 bit OUT TRUE hm2_5i25.0.encoder.03.input-a
5 bit OUT TRUE hm2_5i25.0.encoder.03.input-b
5 bit OUT FALSE hm2_5i25.0.encoder.03.input-index
5 bit IN FALSE hm2_5i25.0.encoder.03.latch-enable
5 bit IN FALSE hm2_5i25.0.encoder.03.latch-polarity
5 float OUT 0 hm2_5i25.0.encoder.03.position
5 float OUT 0 hm2_5i25.0.encoder.03.position-latched
5 bit OUT FALSE hm2_5i25.0.encoder.03.quad-error
5 bit IN FALSE hm2_5i25.0.encoder.03.quad-error-enable
5 s32 OUT 0 hm2_5i25.0.encoder.03.rawcounts
5 s32 OUT 0 hm2_5i25.0.encoder.03.rawlatch
5 bit IN FALSE hm2_5i25.0.encoder.03.reset
5 float OUT 0 hm2_5i25.0.encoder.03.velocity
5 s32 OUT 0 hm2_5i25.0.encoder.04.count
5 s32 OUT 0 hm2_5i25.0.encoder.04.count-latched
5 bit I/O FALSE hm2_5i25.0.encoder.04.index-enable
5 bit OUT TRUE hm2_5i25.0.encoder.04.input-a
5 bit OUT TRUE hm2_5i25.0.encoder.04.input-b
5 bit OUT FALSE hm2_5i25.0.encoder.04.input-index
5 bit IN FALSE hm2_5i25.0.encoder.04.latch-enable
5 bit IN FALSE hm2_5i25.0.encoder.04.latch-polarity
5 float OUT 0 hm2_5i25.0.encoder.04.position
5 float OUT 0 hm2_5i25.0.encoder.04.position-latched
5 bit OUT FALSE hm2_5i25.0.encoder.04.quad-error
5 bit IN FALSE hm2_5i25.0.encoder.04.quad-error-enable
5 s32 OUT 0 hm2_5i25.0.encoder.04.rawcounts
5 s32 OUT 0 hm2_5i25.0.encoder.04.rawlatch
5 bit IN FALSE hm2_5i25.0.encoder.04.reset
5 float OUT 0 hm2_5i25.0.encoder.04.velocity
5 s32 OUT 0 hm2_5i25.0.encoder.05.count
5 s32 OUT 0 hm2_5i25.0.encoder.05.count-latched
5 bit I/O FALSE hm2_5i25.0.encoder.05.index-enable
5 bit OUT TRUE hm2_5i25.0.encoder.05.input-a
5 bit OUT TRUE hm2_5i25.0.encoder.05.input-b
5 bit OUT FALSE hm2_5i25.0.encoder.05.input-index
5 bit IN FALSE hm2_5i25.0.encoder.05.latch-enable
5 bit IN FALSE hm2_5i25.0.encoder.05.latch-polarity
5 float OUT 0 hm2_5i25.0.encoder.05.position
5 float OUT 0 hm2_5i25.0.encoder.05.position-latched
5 bit OUT FALSE hm2_5i25.0.encoder.05.quad-error
5 bit IN FALSE hm2_5i25.0.encoder.05.quad-error-enable
5 s32 OUT 0 hm2_5i25.0.encoder.05.rawcounts
5 s32 OUT 0 hm2_5i25.0.encoder.05.rawlatch
5 bit IN FALSE hm2_5i25.0.encoder.05.reset
5 float OUT 0 hm2_5i25.0.encoder.05.velocity
5 s32 OUT 0 hm2_5i25.0.encoder.06.count
5 s32 OUT 0 hm2_5i25.0.encoder.06.count-latched
5 bit I/O FALSE hm2_5i25.0.encoder.06.index-enable
5 bit OUT TRUE hm2_5i25.0.encoder.06.input-a
5 bit OUT TRUE hm2_5i25.0.encoder.06.input-b
5 bit OUT FALSE hm2_5i25.0.encoder.06.input-index
5 bit IN FALSE hm2_5i25.0.encoder.06.latch-enable
5 bit IN FALSE hm2_5i25.0.encoder.06.latch-polarity
5 float OUT 0 hm2_5i25.0.encoder.06.position
5 float OUT 0 hm2_5i25.0.encoder.06.position-latched
5 bit OUT FALSE hm2_5i25.0.encoder.06.quad-error
5 bit IN FALSE hm2_5i25.0.encoder.06.quad-error-enable
5 s32 OUT 0 hm2_5i25.0.encoder.06.rawcounts
5 s32 OUT 0 hm2_5i25.0.encoder.06.rawlatch
5 bit IN FALSE hm2_5i25.0.encoder.06.reset
5 float OUT 0 hm2_5i25.0.encoder.06.velocity
5 s32 OUT 0 hm2_5i25.0.encoder.07.count
5 s32 OUT 0 hm2_5i25.0.encoder.07.count-latched
5 bit I/O FALSE hm2_5i25.0.encoder.07.index-enable
5 bit OUT TRUE hm2_5i25.0.encoder.07.input-a
5 bit OUT TRUE hm2_5i25.0.encoder.07.input-b
5 bit OUT FALSE hm2_5i25.0.encoder.07.input-index
5 bit IN FALSE hm2_5i25.0.encoder.07.latch-enable
5 bit IN FALSE hm2_5i25.0.encoder.07.latch-polarity
5 float OUT 0 hm2_5i25.0.encoder.07.position
5 float OUT 0 hm2_5i25.0.encoder.07.position-latched
5 bit OUT FALSE hm2_5i25.0.encoder.07.quad-error
5 bit IN FALSE hm2_5i25.0.encoder.07.quad-error-enable
5 s32 OUT 0 hm2_5i25.0.encoder.07.rawcounts
5 s32 OUT 0 hm2_5i25.0.encoder.07.rawlatch
5 bit IN FALSE hm2_5i25.0.encoder.07.reset
5 float OUT 0 hm2_5i25.0.encoder.07.velocity
5 u32 IN 0x007F2815 hm2_5i25.0.encoder.muxed-sample-frequency
5 bit OUT TRUE hm2_5i25.0.gpio.000.in
5 bit OUT FALSE hm2_5i25.0.gpio.000.in_not
5 bit OUT TRUE hm2_5i25.0.gpio.001.in
5 bit OUT FALSE hm2_5i25.0.gpio.001.in_not
5 bit OUT FALSE hm2_5i25.0.gpio.002.in
5 bit OUT TRUE hm2_5i25.0.gpio.002.in_not
5 bit OUT FALSE hm2_5i25.0.gpio.003.in
5 bit OUT TRUE hm2_5i25.0.gpio.003.in_not
5 bit OUT FALSE hm2_5i25.0.gpio.004.in
5 bit OUT TRUE hm2_5i25.0.gpio.004.in_not
5 bit OUT FALSE hm2_5i25.0.gpio.005.in
5 bit OUT TRUE hm2_5i25.0.gpio.005.in_not
5 bit OUT FALSE hm2_5i25.0.gpio.006.in
5 bit OUT TRUE hm2_5i25.0.gpio.006.in_not
5 bit OUT FALSE hm2_5i25.0.gpio.007.in
5 bit OUT TRUE hm2_5i25.0.gpio.007.in_not
5 bit OUT FALSE hm2_5i25.0.gpio.008.in
5 bit OUT TRUE hm2_5i25.0.gpio.008.in_not
5 bit OUT FALSE hm2_5i25.0.gpio.009.in
5 bit OUT TRUE hm2_5i25.0.gpio.009.in_not
5 bit OUT FALSE hm2_5i25.0.gpio.010.in
5 bit OUT TRUE hm2_5i25.0.gpio.010.in_not
5 bit OUT TRUE hm2_5i25.0.gpio.011.in
5 bit OUT FALSE hm2_5i25.0.gpio.011.in_not
5 bit OUT TRUE hm2_5i25.0.gpio.012.in
5 bit OUT FALSE hm2_5i25.0.gpio.012.in_not
5 bit OUT TRUE hm2_5i25.0.gpio.013.in
5 bit OUT FALSE hm2_5i25.0.gpio.013.in_not
5 bit OUT TRUE hm2_5i25.0.gpio.014.in
5 bit OUT FALSE hm2_5i25.0.gpio.014.in_not
5 bit OUT TRUE hm2_5i25.0.gpio.015.in
5 bit OUT FALSE hm2_5i25.0.gpio.015.in_not
5 bit OUT TRUE hm2_5i25.0.gpio.016.in
5 bit OUT FALSE hm2_5i25.0.gpio.016.in_not
5 bit OUT TRUE hm2_5i25.0.gpio.017.in
5 bit OUT FALSE hm2_5i25.0.gpio.017.in_not
5 bit IN FALSE hm2_5i25.0.gpio.017.out
5 bit OUT TRUE hm2_5i25.0.gpio.018.in
5 bit OUT FALSE hm2_5i25.0.gpio.018.in_not
5 bit IN FALSE hm2_5i25.0.gpio.018.out
5 bit OUT FALSE hm2_5i25.0.gpio.019.in
5 bit OUT TRUE hm2_5i25.0.gpio.019.in_not
5 bit OUT FALSE hm2_5i25.0.gpio.020.in
5 bit OUT TRUE hm2_5i25.0.gpio.020.in_not
5 bit OUT FALSE hm2_5i25.0.gpio.021.in
5 bit OUT TRUE hm2_5i25.0.gpio.021.in_not
5 bit OUT FALSE hm2_5i25.0.gpio.022.in
5 bit OUT TRUE hm2_5i25.0.gpio.022.in_not
5 bit OUT FALSE hm2_5i25.0.gpio.023.in
5 bit OUT TRUE hm2_5i25.0.gpio.023.in_not
5 bit OUT FALSE hm2_5i25.0.gpio.024.in
5 bit OUT TRUE hm2_5i25.0.gpio.024.in_not
5 bit OUT FALSE hm2_5i25.0.gpio.025.in
5 bit OUT TRUE hm2_5i25.0.gpio.025.in_not
5 bit OUT FALSE hm2_5i25.0.gpio.026.in
5 bit OUT TRUE hm2_5i25.0.gpio.026.in_not
5 bit OUT TRUE hm2_5i25.0.gpio.027.in
5 bit OUT FALSE hm2_5i25.0.gpio.027.in_not
5 bit OUT TRUE hm2_5i25.0.gpio.028.in
5 bit OUT FALSE hm2_5i25.0.gpio.028.in_not
5 bit OUT TRUE hm2_5i25.0.gpio.029.in
5 bit OUT FALSE hm2_5i25.0.gpio.029.in_not
5 bit OUT TRUE hm2_5i25.0.gpio.030.in
5 bit OUT FALSE hm2_5i25.0.gpio.030.in_not
5 bit OUT TRUE hm2_5i25.0.gpio.031.in
5 bit OUT FALSE hm2_5i25.0.gpio.031.in_not
5 bit OUT TRUE hm2_5i25.0.gpio.032.in
5 bit OUT FALSE hm2_5i25.0.gpio.032.in_not
5 bit OUT TRUE hm2_5i25.0.gpio.033.in
5 bit OUT FALSE hm2_5i25.0.gpio.033.in_not
5 bit IN FALSE hm2_5i25.0.led.CR01
5 bit IN FALSE hm2_5i25.0.led.CR02
5 bit IN FALSE hm2_5i25.0.pwmgen.00.enable
5 float IN 0 hm2_5i25.0.pwmgen.00.value
5 bit IN FALSE hm2_5i25.0.pwmgen.01.enable
5 float IN 0 hm2_5i25.0.pwmgen.01.value
5 s32 OUT 0 hm2_5i25.0.read.time
5 s32 OUT 0 hm2_5i25.0.read_gpio.time
5 u32 OUT 0x00000000 hm2_5i25.0.sserial.port-0.fault-count
5 u32 OUT 0x00000000 hm2_5i25.0.sserial.port-0.port_state
5 bit IN TRUE hm2_5i25.0.sserial.port-0.run
5 bit IN FALSE hm2_5i25.0.stepgen.00.control-type
5 s32 OUT 0 hm2_5i25.0.stepgen.00.counts
5 float OUT 0 hm2_5i25.0.stepgen.00.dbg_err_at_match
5 float OUT 0 hm2_5i25.0.stepgen.00.dbg_ff_vel
5 float OUT 0 hm2_5i25.0.stepgen.00.dbg_pos_minus_prev_cmd
5 float OUT 0 hm2_5i25.0.stepgen.00.dbg_s_to_match
5 s32 OUT 0 hm2_5i25.0.stepgen.00.dbg_step_rate
5 float OUT 0 hm2_5i25.0.stepgen.00.dbg_vel_error
5 bit IN FALSE hm2_5i25.0.stepgen.00.enable
5 float IN 0 hm2_5i25.0.stepgen.00.position-cmd
5 float OUT 0 hm2_5i25.0.stepgen.00.position-fb
5 float IN 0 hm2_5i25.0.stepgen.00.velocity-cmd
5 float OUT 0 hm2_5i25.0.stepgen.00.velocity-fb
5 bit IN FALSE hm2_5i25.0.stepgen.01.control-type
5 s32 OUT 0 hm2_5i25.0.stepgen.01.counts
5 float OUT 0 hm2_5i25.0.stepgen.01.dbg_err_at_match
5 float OUT 0 hm2_5i25.0.stepgen.01.dbg_ff_vel
5 float OUT 0 hm2_5i25.0.stepgen.01.dbg_pos_minus_prev_cmd
5 float OUT 0 hm2_5i25.0.stepgen.01.dbg_s_to_match
5 s32 OUT 0 hm2_5i25.0.stepgen.01.dbg_step_rate
5 float OUT 0 hm2_5i25.0.stepgen.01.dbg_vel_error
5 bit IN FALSE hm2_5i25.0.stepgen.01.enable
5 float IN 0 hm2_5i25.0.stepgen.01.position-cmd
5 float OUT 0 hm2_5i25.0.stepgen.01.position-fb
5 float IN 0 hm2_5i25.0.stepgen.01.velocity-cmd
5 float OUT 0 hm2_5i25.0.stepgen.01.velocity-fb
5 bit IN FALSE hm2_5i25.0.stepgen.02.control-type
5 s32 OUT 0 hm2_5i25.0.stepgen.02.counts
5 float OUT 0 hm2_5i25.0.stepgen.02.dbg_err_at_match
5 float OUT 0 hm2_5i25.0.stepgen.02.dbg_ff_vel
5 float OUT 0 hm2_5i25.0.stepgen.02.dbg_pos_minus_prev_cmd
5 float OUT 0 hm2_5i25.0.stepgen.02.dbg_s_to_match
5 s32 OUT 0 hm2_5i25.0.stepgen.02.dbg_step_rate
5 float OUT 0 hm2_5i25.0.stepgen.02.dbg_vel_error
5 bit IN FALSE hm2_5i25.0.stepgen.02.enable
5 float IN 0 hm2_5i25.0.stepgen.02.position-cmd
5 float OUT 0 hm2_5i25.0.stepgen.02.position-fb
5 float IN 0 hm2_5i25.0.stepgen.02.velocity-cmd
5 float OUT 0 hm2_5i25.0.stepgen.02.velocity-fb
5 bit IN FALSE hm2_5i25.0.stepgen.03.control-type
5 s32 OUT 0 hm2_5i25.0.stepgen.03.counts
5 float OUT 0 hm2_5i25.0.stepgen.03.dbg_err_at_match
5 float OUT 0 hm2_5i25.0.stepgen.03.dbg_ff_vel
5 float OUT 0 hm2_5i25.0.stepgen.03.dbg_pos_minus_prev_cmd
5 float OUT 0 hm2_5i25.0.stepgen.03.dbg_s_to_match
5 s32 OUT 0 hm2_5i25.0.stepgen.03.dbg_step_rate
5 float OUT 0 hm2_5i25.0.stepgen.03.dbg_vel_error
5 bit IN FALSE hm2_5i25.0.stepgen.03.enable
5 float IN 0 hm2_5i25.0.stepgen.03.position-cmd
5 float OUT 0 hm2_5i25.0.stepgen.03.position-fb
5 float IN 0 hm2_5i25.0.stepgen.03.velocity-cmd
5 float OUT 0 hm2_5i25.0.stepgen.03.velocity-fb
5 bit IN FALSE hm2_5i25.0.stepgen.04.control-type
5 s32 OUT 0 hm2_5i25.0.stepgen.04.counts
5 float OUT 0 hm2_5i25.0.stepgen.04.dbg_err_at_match
5 float OUT 0 hm2_5i25.0.stepgen.04.dbg_ff_vel
5 float OUT 0 hm2_5i25.0.stepgen.04.dbg_pos_minus_prev_cmd
5 float OUT 0 hm2_5i25.0.stepgen.04.dbg_s_to_match
5 s32 OUT 0 hm2_5i25.0.stepgen.04.dbg_step_rate
5 float OUT 0 hm2_5i25.0.stepgen.04.dbg_vel_error
5 bit IN FALSE hm2_5i25.0.stepgen.04.enable
5 float IN 0 hm2_5i25.0.stepgen.04.position-cmd
5 float OUT 0 hm2_5i25.0.stepgen.04.position-fb
5 float IN 0 hm2_5i25.0.stepgen.04.velocity-cmd
5 float OUT 0 hm2_5i25.0.stepgen.04.velocity-fb
5 bit IN FALSE hm2_5i25.0.stepgen.05.control-type
5 s32 OUT 0 hm2_5i25.0.stepgen.05.counts
5 float OUT 0 hm2_5i25.0.stepgen.05.dbg_err_at_match
5 float OUT 0 hm2_5i25.0.stepgen.05.dbg_ff_vel
5 float OUT 0 hm2_5i25.0.stepgen.05.dbg_pos_minus_prev_cmd
5 float OUT 0 hm2_5i25.0.stepgen.05.dbg_s_to_match
5 s32 OUT 0 hm2_5i25.0.stepgen.05.dbg_step_rate
5 float OUT 0 hm2_5i25.0.stepgen.05.dbg_vel_error
5 bit IN FALSE hm2_5i25.0.stepgen.05.enable
5 float IN 0 hm2_5i25.0.stepgen.05.position-cmd
5 float OUT 0 hm2_5i25.0.stepgen.05.position-fb
5 float IN 0 hm2_5i25.0.stepgen.05.velocity-cmd
5 float OUT 0 hm2_5i25.0.stepgen.05.velocity-fb
5 bit IN FALSE hm2_5i25.0.stepgen.06.control-type
5 s32 OUT 0 hm2_5i25.0.stepgen.06.counts
5 float OUT 0 hm2_5i25.0.stepgen.06.dbg_err_at_match
5 float OUT 0 hm2_5i25.0.stepgen.06.dbg_ff_vel
5 float OUT 0 hm2_5i25.0.stepgen.06.dbg_pos_minus_prev_cmd
5 float OUT 0 hm2_5i25.0.stepgen.06.dbg_s_to_match
5 s32 OUT 0 hm2_5i25.0.stepgen.06.dbg_step_rate
5 float OUT 0 hm2_5i25.0.stepgen.06.dbg_vel_error
5 bit IN FALSE hm2_5i25.0.stepgen.06.enable
5 float IN 0 hm2_5i25.0.stepgen.06.position-cmd
5 float OUT 0 hm2_5i25.0.stepgen.06.position-fb
5 float IN 0 hm2_5i25.0.stepgen.06.velocity-cmd
5 float OUT 0 hm2_5i25.0.stepgen.06.velocity-fb
5 bit IN FALSE hm2_5i25.0.stepgen.07.control-type
5 s32 OUT 0 hm2_5i25.0.stepgen.07.counts
5 float OUT 0 hm2_5i25.0.stepgen.07.dbg_err_at_match
5 float OUT 0 hm2_5i25.0.stepgen.07.dbg_ff_vel
5 float OUT 0 hm2_5i25.0.stepgen.07.dbg_pos_minus_prev_cmd
5 float OUT 0 hm2_5i25.0.stepgen.07.dbg_s_to_match
5 s32 OUT 0 hm2_5i25.0.stepgen.07.dbg_step_rate
5 float OUT 0 hm2_5i25.0.stepgen.07.dbg_vel_error
5 bit IN FALSE hm2_5i25.0.stepgen.07.enable
5 float IN 0 hm2_5i25.0.stepgen.07.position-cmd
5 float OUT 0 hm2_5i25.0.stepgen.07.position-fb
5 float IN 0 hm2_5i25.0.stepgen.07.velocity-cmd
5 float OUT 0 hm2_5i25.0.stepgen.07.velocity-fb
5 bit I/O FALSE hm2_5i25.0.watchdog.has_bit
5 s32 OUT 0 hm2_5i25.0.write.time
5 s32 OUT 0 hm2_5i25.0.write_gpio.time
halcmd: show param
Parameters:
Owner Type Dir Value Name
5 u32 RO 0x00000009 hm2_5i25.0.7i84.0.0.nvbaudrate
5 u32 RO 0x00000000 hm2_5i25.0.7i84.0.0.nvencmode0
5 u32 RO 0x00000000 hm2_5i25.0.7i84.0.0.nvencmode1
5 u32 RO 0x18000021 hm2_5i25.0.7i84.0.0.nvunitnumber
5 u32 RO 0x00000032 hm2_5i25.0.7i84.0.0.nvwatchdogtimeout
5 bit RW FALSE hm2_5i25.0.7i84.0.0.output-00-invert
5 bit RW FALSE hm2_5i25.0.7i84.0.0.output-01-invert
5 bit RW FALSE hm2_5i25.0.7i84.0.0.output-02-invert
5 bit RW FALSE hm2_5i25.0.7i84.0.0.output-03-invert
5 bit RW FALSE hm2_5i25.0.7i84.0.0.output-04-invert
5 bit RW FALSE hm2_5i25.0.7i84.0.0.output-05-invert
5 bit RW FALSE hm2_5i25.0.7i84.0.0.output-06-invert
5 bit RW FALSE hm2_5i25.0.7i84.0.0.output-07-invert
5 bit RW FALSE hm2_5i25.0.7i84.0.0.output-08-invert
5 bit RW FALSE hm2_5i25.0.7i84.0.0.output-09-invert
5 bit RW FALSE hm2_5i25.0.7i84.0.0.output-10-invert
5 bit RW FALSE hm2_5i25.0.7i84.0.0.output-11-invert
5 bit RW FALSE hm2_5i25.0.7i84.0.0.output-12-invert
5 bit RW FALSE hm2_5i25.0.7i84.0.0.output-13-invert
5 bit RW FALSE hm2_5i25.0.7i84.0.0.output-14-invert
5 bit RW FALSE hm2_5i25.0.7i84.0.0.output-15-invert
5 u32 RO 0x0000000E hm2_5i25.0.7i84.0.0.swrevision
5 bit RW FALSE hm2_5i25.0.encoder.00.counter-mode
5 bit RW TRUE hm2_5i25.0.encoder.00.filter
5 bit RW FALSE hm2_5i25.0.encoder.00.index-invert
5 bit RW FALSE hm2_5i25.0.encoder.00.index-mask
5 bit RW FALSE hm2_5i25.0.encoder.00.index-mask-invert
5 float RW 1 hm2_5i25.0.encoder.00.scale
5 float RW 0.5 hm2_5i25.0.encoder.00.vel-timeout
5 bit RW FALSE hm2_5i25.0.encoder.01.counter-mode
5 bit RW TRUE hm2_5i25.0.encoder.01.filter
5 bit RW FALSE hm2_5i25.0.encoder.01.index-invert
5 bit RW FALSE hm2_5i25.0.encoder.01.index-mask
5 bit RW FALSE hm2_5i25.0.encoder.01.index-mask-invert
5 float RW 1 hm2_5i25.0.encoder.01.scale
5 float RW 0.5 hm2_5i25.0.encoder.01.vel-timeout
5 bit RW FALSE hm2_5i25.0.encoder.02.counter-mode
5 bit RW TRUE hm2_5i25.0.encoder.02.filter
5 bit RW FALSE hm2_5i25.0.encoder.02.index-invert
5 bit RW FALSE hm2_5i25.0.encoder.02.index-mask
5 bit RW FALSE hm2_5i25.0.encoder.02.index-mask-invert
5 float RW 1 hm2_5i25.0.encoder.02.scale
5 float RW 0.5 hm2_5i25.0.encoder.02.vel-timeout
5 bit RW FALSE hm2_5i25.0.encoder.03.counter-mode
5 bit RW TRUE hm2_5i25.0.encoder.03.filter
5 bit RW FALSE hm2_5i25.0.encoder.03.index-invert
5 bit RW FALSE hm2_5i25.0.encoder.03.index-mask
5 bit RW FALSE hm2_5i25.0.encoder.03.index-mask-invert
5 float RW 1 hm2_5i25.0.encoder.03.scale
5 float RW 0.5 hm2_5i25.0.encoder.03.vel-timeout
5 bit RW FALSE hm2_5i25.0.encoder.04.counter-mode
5 bit RW TRUE hm2_5i25.0.encoder.04.filter
5 bit RW FALSE hm2_5i25.0.encoder.04.index-invert
5 bit RW FALSE hm2_5i25.0.encoder.04.index-mask
5 bit RW FALSE hm2_5i25.0.encoder.04.index-mask-invert
5 float RW 1 hm2_5i25.0.encoder.04.scale
5 float RW 0.5 hm2_5i25.0.encoder.04.vel-timeout
5 bit RW FALSE hm2_5i25.0.encoder.05.counter-mode
5 bit RW TRUE hm2_5i25.0.encoder.05.filter
5 bit RW FALSE hm2_5i25.0.encoder.05.index-invert
5 bit RW FALSE hm2_5i25.0.encoder.05.index-mask
5 bit RW FALSE hm2_5i25.0.encoder.05.index-mask-invert
5 float RW 1 hm2_5i25.0.encoder.05.scale
5 float RW 0.5 hm2_5i25.0.encoder.05.vel-timeout
5 bit RW FALSE hm2_5i25.0.encoder.06.counter-mode
5 bit RW TRUE hm2_5i25.0.encoder.06.filter
5 bit RW FALSE hm2_5i25.0.encoder.06.index-invert
5 bit RW FALSE hm2_5i25.0.encoder.06.index-mask
5 bit RW FALSE hm2_5i25.0.encoder.06.index-mask-invert
5 float RW 1 hm2_5i25.0.encoder.06.scale
5 float RW 0.5 hm2_5i25.0.encoder.06.vel-timeout
5 bit RW FALSE hm2_5i25.0.encoder.07.counter-mode
5 bit RW TRUE hm2_5i25.0.encoder.07.filter
5 bit RW FALSE hm2_5i25.0.encoder.07.index-invert
5 bit RW FALSE hm2_5i25.0.encoder.07.index-mask
5 bit RW FALSE hm2_5i25.0.encoder.07.index-mask-invert
5 float RW 1 hm2_5i25.0.encoder.07.scale
5 float RW 0.5 hm2_5i25.0.encoder.07.vel-timeout
5 bit RW FALSE hm2_5i25.0.gpio.001.invert_output
5 bit RW FALSE hm2_5i25.0.gpio.001.is_opendrain
5 bit RW FALSE hm2_5i25.0.gpio.002.invert_output
5 bit RW FALSE hm2_5i25.0.gpio.002.is_opendrain
5 bit RW FALSE hm2_5i25.0.gpio.003.invert_output
5 bit RW FALSE hm2_5i25.0.gpio.003.is_opendrain
5 bit RW FALSE hm2_5i25.0.gpio.004.invert_output
5 bit RW FALSE hm2_5i25.0.gpio.004.is_opendrain
5 bit RW FALSE hm2_5i25.0.gpio.005.invert_output
5 bit RW FALSE hm2_5i25.0.gpio.005.is_opendrain
5 bit RW FALSE hm2_5i25.0.gpio.006.invert_output
5 bit RW FALSE hm2_5i25.0.gpio.006.is_opendrain
5 bit RW FALSE hm2_5i25.0.gpio.007.invert_output
5 bit RW FALSE hm2_5i25.0.gpio.007.is_opendrain
5 bit RW FALSE hm2_5i25.0.gpio.008.invert_output
5 bit RW FALSE hm2_5i25.0.gpio.008.is_opendrain
5 bit RW FALSE hm2_5i25.0.gpio.009.invert_output
5 bit RW FALSE hm2_5i25.0.gpio.009.is_opendrain
5 bit RW FALSE hm2_5i25.0.gpio.010.invert_output
5 bit RW FALSE hm2_5i25.0.gpio.010.is_opendrain
5 bit RW FALSE hm2_5i25.0.gpio.017.invert_output
5 bit RW FALSE hm2_5i25.0.gpio.017.is_opendrain
5 bit RW FALSE hm2_5i25.0.gpio.017.is_output
5 bit RW FALSE hm2_5i25.0.gpio.018.invert_output
5 bit RW FALSE hm2_5i25.0.gpio.018.is_opendrain
5 bit RW FALSE hm2_5i25.0.gpio.018.is_output
5 bit RW FALSE hm2_5i25.0.gpio.019.invert_output
5 bit RW FALSE hm2_5i25.0.gpio.019.is_opendrain
5 bit RW FALSE hm2_5i25.0.gpio.020.invert_output
5 bit RW FALSE hm2_5i25.0.gpio.020.is_opendrain
5 bit RW FALSE hm2_5i25.0.gpio.021.invert_output
5 bit RW FALSE hm2_5i25.0.gpio.021.is_opendrain
5 bit RW FALSE hm2_5i25.0.gpio.022.invert_output
5 bit RW FALSE hm2_5i25.0.gpio.022.is_opendrain
5 bit RW FALSE hm2_5i25.0.gpio.023.invert_output
5 bit RW FALSE hm2_5i25.0.gpio.023.is_opendrain
5 bit RW FALSE hm2_5i25.0.gpio.024.invert_output
5 bit RW FALSE hm2_5i25.0.gpio.024.is_opendrain
5 bit RW FALSE hm2_5i25.0.gpio.025.invert_output
5 bit RW FALSE hm2_5i25.0.gpio.025.is_opendrain
5 bit RW FALSE hm2_5i25.0.gpio.026.invert_output
5 bit RW FALSE hm2_5i25.0.gpio.026.is_opendrain
5 bit RW FALSE hm2_5i25.0.gpio.027.invert_output
5 bit RW FALSE hm2_5i25.0.gpio.027.is_opendrain
5 bit RW FALSE hm2_5i25.0.io_error
5 s32 RW 1 hm2_5i25.0.pwmgen.00.output-type
5 float RW 1 hm2_5i25.0.pwmgen.00.scale
5 s32 RW 1 hm2_5i25.0.pwmgen.01.output-type
5 float RW 1 hm2_5i25.0.pwmgen.01.scale
5 u32 RW 0x00004E20 hm2_5i25.0.pwmgen.pdm_frequency
5 u32 RW 0x00004E20 hm2_5i25.0.pwmgen.pwm_frequency
5 s32 RW 0 hm2_5i25.0.read.tmax
5 bit RO FALSE hm2_5i25.0.read.tmax-increased
5 s32 RW 0 hm2_5i25.0.read_gpio.tmax
5 bit RO FALSE hm2_5i25.0.read_gpio.tmax-increased
5 u32 RW 0x00000001 hm2_5i25.0.sserial.port-0.fault-dec
5 u32 RW 0x0000000A hm2_5i25.0.sserial.port-0.fault-inc
5 u32 RW 0x000000C8 hm2_5i25.0.sserial.port-0.fault-lim
5 u32 RW 0x00077FE2 hm2_5i25.0.stepgen.00.dirhold
5 u32 RW 0x00077FE2 hm2_5i25.0.stepgen.00.dirsetup
5 float RW 1 hm2_5i25.0.stepgen.00.maxaccel
5 float RW 0 hm2_5i25.0.stepgen.00.maxvel
5 float RW 1 hm2_5i25.0.stepgen.00.position-scale
5 u32 RW 0x00000000 hm2_5i25.0.stepgen.00.step_type
5 u32 RW 0x00077FE2 hm2_5i25.0.stepgen.00.steplen
5 u32 RW 0x00077FE2 hm2_5i25.0.stepgen.00.stepspace
5 u32 RW 0x00000000 hm2_5i25.0.stepgen.00.table-data-0
5 u32 RW 0x00000000 hm2_5i25.0.stepgen.00.table-data-1
5 u32 RW 0x00000000 hm2_5i25.0.stepgen.00.table-data-2
5 u32 RW 0x00000000 hm2_5i25.0.stepgen.00.table-data-3
5 u32 RW 0x00077FE2 hm2_5i25.0.stepgen.01.dirhold
5 u32 RW 0x00077FE2 hm2_5i25.0.stepgen.01.dirsetup
5 float RW 1 hm2_5i25.0.stepgen.01.maxaccel
5 float RW 0 hm2_5i25.0.stepgen.01.maxvel
5 float RW 1 hm2_5i25.0.stepgen.01.position-scale
5 u32 RW 0x00000000 hm2_5i25.0.stepgen.01.step_type
5 u32 RW 0x00077FE2 hm2_5i25.0.stepgen.01.steplen
5 u32 RW 0x00077FE2 hm2_5i25.0.stepgen.01.stepspace
5 u32 RW 0x00000000 hm2_5i25.0.stepgen.01.table-data-0
5 u32 RW 0x00000000 hm2_5i25.0.stepgen.01.table-data-1
5 u32 RW 0x00000000 hm2_5i25.0.stepgen.01.table-data-2
5 u32 RW 0x00000000 hm2_5i25.0.stepgen.01.table-data-3
5 u32 RW 0x00077FE2 hm2_5i25.0.stepgen.02.dirhold
5 u32 RW 0x00077FE2 hm2_5i25.0.stepgen.02.dirsetup
5 float RW 1 hm2_5i25.0.stepgen.02.maxaccel
5 float RW 0 hm2_5i25.0.stepgen.02.maxvel
5 float RW 1 hm2_5i25.0.stepgen.02.position-scale
5 u32 RW 0x00000000 hm2_5i25.0.stepgen.02.step_type
5 u32 RW 0x00077FE2 hm2_5i25.0.stepgen.02.steplen
5 u32 RW 0x00077FE2 hm2_5i25.0.stepgen.02.stepspace
5 u32 RW 0x00000000 hm2_5i25.0.stepgen.02.table-data-0
5 u32 RW 0x00000000 hm2_5i25.0.stepgen.02.table-data-1
5 u32 RW 0x00000000 hm2_5i25.0.stepgen.02.table-data-2
5 u32 RW 0x00000000 hm2_5i25.0.stepgen.02.table-data-3
5 u32 RW 0x00077FE2 hm2_5i25.0.stepgen.03.dirhold
5 u32 RW 0x00077FE2 hm2_5i25.0.stepgen.03.dirsetup
5 float RW 1 hm2_5i25.0.stepgen.03.maxaccel
5 float RW 0 hm2_5i25.0.stepgen.03.maxvel
5 float RW 1 hm2_5i25.0.stepgen.03.position-scale
5 u32 RW 0x00000000 hm2_5i25.0.stepgen.03.step_type
5 u32 RW 0x00077FE2 hm2_5i25.0.stepgen.03.steplen
5 u32 RW 0x00077FE2 hm2_5i25.0.stepgen.03.stepspace
5 u32 RW 0x00077FE2 hm2_5i25.0.stepgen.04.dirhold
5 u32 RW 0x00077FE2 hm2_5i25.0.stepgen.04.dirsetup
5 float RW 1 hm2_5i25.0.stepgen.04.maxaccel
5 float RW 0 hm2_5i25.0.stepgen.04.maxvel
5 float RW 1 hm2_5i25.0.stepgen.04.position-scale
5 u32 RW 0x00000000 hm2_5i25.0.stepgen.04.step_type
5 u32 RW 0x00077FE2 hm2_5i25.0.stepgen.04.steplen
5 u32 RW 0x00077FE2 hm2_5i25.0.stepgen.04.stepspace
5 u32 RW 0x00000000 hm2_5i25.0.stepgen.04.table-data-0
5 u32 RW 0x00000000 hm2_5i25.0.stepgen.04.table-data-1
5 u32 RW 0x00000000 hm2_5i25.0.stepgen.04.table-data-2
5 u32 RW 0x00000000 hm2_5i25.0.stepgen.04.table-data-3
5 u32 RW 0x00077FE2 hm2_5i25.0.stepgen.05.dirhold
5 u32 RW 0x00077FE2 hm2_5i25.0.stepgen.05.dirsetup
5 float RW 1 hm2_5i25.0.stepgen.05.maxaccel
5 float RW 0 hm2_5i25.0.stepgen.05.maxvel
5 float RW 1 hm2_5i25.0.stepgen.05.position-scale
5 u32 RW 0x00000000 hm2_5i25.0.stepgen.05.step_type
5 u32 RW 0x00077FE2 hm2_5i25.0.stepgen.05.steplen
5 u32 RW 0x00077FE2 hm2_5i25.0.stepgen.05.stepspace
5 u32 RW 0x00000000 hm2_5i25.0.stepgen.05.table-data-0
5 u32 RW 0x00000000 hm2_5i25.0.stepgen.05.table-data-1
5 u32 RW 0x00000000 hm2_5i25.0.stepgen.05.table-data-2
5 u32 RW 0x00000000 hm2_5i25.0.stepgen.05.table-data-3
5 u32 RW 0x00077FE2 hm2_5i25.0.stepgen.06.dirhold
5 u32 RW 0x00077FE2 hm2_5i25.0.stepgen.06.dirsetup
5 float RW 1 hm2_5i25.0.stepgen.06.maxaccel
5 float RW 0 hm2_5i25.0.stepgen.06.maxvel
5 float RW 1 hm2_5i25.0.stepgen.06.position-scale
5 u32 RW 0x00000000 hm2_5i25.0.stepgen.06.step_type
5 u32 RW 0x00077FE2 hm2_5i25.0.stepgen.06.steplen
5 u32 RW 0x00077FE2 hm2_5i25.0.stepgen.06.stepspace
5 u32 RW 0x00000000 hm2_5i25.0.stepgen.06.table-data-0
5 u32 RW 0x00000000 hm2_5i25.0.stepgen.06.table-data-1
5 u32 RW 0x00000000 hm2_5i25.0.stepgen.06.table-data-2
5 u32 RW 0x00000000 hm2_5i25.0.stepgen.06.table-data-3
5 u32 RW 0x00077FE2 hm2_5i25.0.stepgen.07.dirhold
5 u32 RW 0x00077FE2 hm2_5i25.0.stepgen.07.dirsetup
5 float RW 1 hm2_5i25.0.stepgen.07.maxaccel
5 float RW 0 hm2_5i25.0.stepgen.07.maxvel
5 float RW 1 hm2_5i25.0.stepgen.07.position-scale
5 u32 RW 0x00000000 hm2_5i25.0.stepgen.07.step_type
5 u32 RW 0x00077FE2 hm2_5i25.0.stepgen.07.steplen
5 u32 RW 0x00077FE2 hm2_5i25.0.stepgen.07.stepspace
5 u32 RW 0x004C4B40 hm2_5i25.0.watchdog.timeout_ns
5 s32 RW 0 hm2_5i25.0.write.tmax
5 bit RO FALSE hm2_5i25.0.write.tmax-increased
5 s32 RW 0 hm2_5i25.0.write_gpio.tmax
5 bit RO FALSE hm2_5i25.0.write_gpio.tmax-increased
halcmd:
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10 Nov 2015 10:34 - 10 Nov 2015 10:40 #65066
by andypugh
Replied by andypugh on topic Spinx1 to 7i85
Your message came in at 0143 my time, hence the delay.
The output is truncated, the pins start at encoder.02, so I am having to guess what the 7i84 GPIO pins are called
If you look at the pin list you will see the new HAL pins/params
5 bit IN FALSE hm2_5i25.0.pwmgen.00.enable
5 float IN 0 hm2_5i25.0.pwmgen.00.value
5 bit IN FALSE hm2_5i25.0.pwmgen.01.enable
5 float IN 0 hm2_5i25.0.pwmgen.01.value
and
5 s32 RW 1 hm2_5i25.0.pwmgen.00.output-type
5 float RW 1 hm2_5i25.0.pwmgen.00.scale
5 s32 RW 1 hm2_5i25.0.pwmgen.01.output-type
5 float RW 1 hm2_5i25.0.pwmgen.01.scale
pwmgen.01 is probably on the internal header, ans pwmgen.00 will be the one where the stepper used to be.
You will use a GPIO pin to operate the enable.
the motion pins are documented here: linuxcnc.org/docs/html/man/man9/motion.9.html
The output is truncated, the pins start at encoder.02, so I am having to guess what the 7i84 GPIO pins are called
If you look at the pin list you will see the new HAL pins/params
5 bit IN FALSE hm2_5i25.0.pwmgen.00.enable
5 float IN 0 hm2_5i25.0.pwmgen.00.value
5 bit IN FALSE hm2_5i25.0.pwmgen.01.enable
5 float IN 0 hm2_5i25.0.pwmgen.01.value
and
5 s32 RW 1 hm2_5i25.0.pwmgen.00.output-type
5 float RW 1 hm2_5i25.0.pwmgen.00.scale
5 s32 RW 1 hm2_5i25.0.pwmgen.01.output-type
5 float RW 1 hm2_5i25.0.pwmgen.01.scale
pwmgen.01 is probably on the internal header, ans pwmgen.00 will be the one where the stepper used to be.
You will use a GPIO pin to operate the enable.
the motion pins are documented here: linuxcnc.org/docs/html/man/man9/motion.9.html
# pwm / dir mode and PWM rather than PDM
setp hm2_5i25.0.pwmgen.00.output-type 1
# this should be the spindle speed at 10V output, ie max spindle speed
setp hm2_5i25.0.pwmgen.00.scale 2500
# set the PWM frequency to 5kHz
setp hm2_5i25.0.pwmgen.pwm_frequency 5000
# connect the spindle speed command to the pwmgen
net spindle-speed motion.spindle-speed-out => hm2_5i25.0.pwmgen.00.value
# connect the spindle enable to GPIO 0. You can change this
net spindle-enable motion.spindle-on => hm2_5i25.0.7i84.0.0.output-00
# the SPINX1 has a /enable (low to enable)
setp hm2_5i25.0.7i84.0.0.output-00-invert 1
Last edit: 10 Nov 2015 10:40 by andypugh.
The following user(s) said Thank You: OT-CNC
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10 Nov 2015 15:46 #65077
by OT-CNC
Replied by OT-CNC on topic Spinx1 to 7i85
The time stamp looks correct for England. I'm in New York so 8:45 pm or so is about right for when I sent it. Oddly the time stamps do not show the correct local time anymore. No delay on your end, I appreciate your quick responses!
I will implement what you outlined.
The 7i84 gpio's are all on 24v so I'm stuck with the 5i25 second unused connector for 5v output signals which I don't want to use as my computer does not have an extra spot to mount a connector without hacking the case. I can do that if I can't find another workaround.
Since this is a lathe and I'm using X and Z, could the unused Y step pin be used for an enable?
I will implement what you outlined.
The 7i84 gpio's are all on 24v so I'm stuck with the 5i25 second unused connector for 5v output signals which I don't want to use as my computer does not have an extra spot to mount a connector without hacking the case. I can do that if I can't find another workaround.
Since this is a lathe and I'm using X and Z, could the unused Y step pin be used for an enable?
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10 Nov 2015 16:16 #65078
by PCW
Replied by PCW on topic Spinx1 to 7i85
Sure, if you only enable 2 stepgens in the hal file (stepgen 0 and 1),
stepgen 2s pins are available as GPIO
stepgen 2s pins are available as GPIO
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10 Nov 2015 16:33 #65079
by andypugh
Yes, you have 4 step/dir pairs per connector, and if you set num_stepgens=2 in the config then all 4 of those pins (on each header) become available as GPIO.
If you compare the show params list above with a similar one done after the config change you will see some "is-output" paramters appear which will help you spot which HAL pins are your newly-available GPIO pins.
Ah, and you need to "setp" them to outputs too.
Replied by andypugh on topic Spinx1 to 7i85
Since this is a lathe and I'm using X and Z, could the unused Y step pin be used for an enable?
Yes, you have 4 step/dir pairs per connector, and if you set num_stepgens=2 in the config then all 4 of those pins (on each header) become available as GPIO.
If you compare the show params list above with a similar one done after the config change you will see some "is-output" paramters appear which will help you spot which HAL pins are your newly-available GPIO pins.
Ah, and you need to "setp" them to outputs too.
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