Flash a XC6SLX9 dev board as a 7i90HD

The proper card type (you should really use your own name here) and pinout file must be included in the top level file

In addition, any source file used must be added to the project
(right click in file window and add if they are not listed)

PCW, a bit off topic.
but i was wondering... there's no PCI setup/hold timing constraints in the 5i25.ucf or elsewhere. how do you get away without them?

They should be there, my oversight, though its not really possible to violate the
PCI specs rather generous 7 ns setup, 0 ns hold and 11 ns output offset specs at 33 MHz with one wait state.

Also the Async TRDY, DEVSEL and STOP signals should have pad-pad times
(more likely to be an issue at 66MHz)

I will look into adding these

thank you for clarification! have to study your PCI implementation... my PCI core implementation attempt effortlessly miss that generous 11ns output offset budget by 3ns on AD pins. among other less severe violations

I want to thank you again PCW.
I read 2 books on VHDL and i understood a little bit more the code, and it's beatifully written.
Now i can compile every firmware i want, i'm better with ISE.

I discovered many things during these fews days, i really thing that my boad has a counterfeit XC6SLX9. You can find it for 3$ in China maybe less if ordered in quantity. That's why you could have this dev board for less than 20$. So my advice is to avoid this kind of products.
So i decided to create my own design with a genuine XC6SLX9-2TQG144C, totally open source to make my experimentations with MCU. It's a really simple board with simple specifications : 100x100mm 2 layers, 72 I/O on 3 connectors (mesa daughter compatible) with 3x FST16211, a SPI interface and a 16Mbit flash.
Since i'm not familiar with FPGA i'll need your help to correct my mistakes.

After reading the FST16211 datasheet i think I inverted I/O, how can i drive enable pins too ?
Do i have to protect the SPI too ? Maybe with a 8bits TTL like the FST16211 ?
And many other questions like what's the use of these pins :
_ pin 37
_ pin 59
_ pin 60
_ pin 69
_ pin 67
_ pin 73
_ pin 144

I don't know if this is any use, but I found this
numato.com/product/mimas-spartan-6-fpga-development-board

And the design files here

github.com/numato/samplecode/tree/master/FPGA/Mimas

Thank you
I already checked these schematics like many other XC6SLX9 dev boards but it's not helping for this specific use.

Regarding Pins

Is this of any help ?
www.xilinx.com/support/documentation/use...es/ug385.pdf#page=19

A little bit thank you. I will follow the same specifications as my dev board for these pins.
I will need advices for the 50mhz crystal too

I think you will have to read the Xilinx docs.....especially UG393 regarding PCB design, there's quite a few docs to go through.

Not as straight forward as designing for a simple adruino type project. Keep going you have an interesting project going on.