Flash a XC6SLX9 dev board as a 7i90HD

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25 Apr 2019 20:29 #131883 by PCW
The proper card type (you should really use your own name here) and pinout file must be included in the top level file

In addition, any source file used must be added to the project
(right click in file window and add if they are not listed)

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25 Apr 2019 22:50 #131897 by dm17ry
PCW, a bit off topic.
but i was wondering... there's no PCI setup/hold timing constraints in the 5i25.ucf or elsewhere. how do you get away without them?

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25 Apr 2019 23:50 - 25 Apr 2019 23:54 #131904 by PCW
They should be there, my oversight, though its not really possible to violate the
PCI specs rather generous 7 ns setup, 0 ns hold and 11 ns output offset specs at 33 MHz with one wait state.

Also the Async TRDY, DEVSEL and STOP signals should have pad-pad times
(more likely to be an issue at 66MHz)

I will look into adding these
Last edit: 25 Apr 2019 23:54 by PCW.

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26 Apr 2019 00:36 - 26 Apr 2019 00:41 #131910 by dm17ry
thank you for clarification! have to study your PCI implementation... my PCI core implementation attempt effortlessly miss that generous 11ns output offset budget by 3ns on AD pins. among other less severe violations :)
Last edit: 26 Apr 2019 00:41 by dm17ry.

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02 May 2019 09:09 - 02 May 2019 09:34 #132498 by gtt38
I want to thank you again PCW.
I read 2 books on VHDL and i understood a little bit more the code, and it's beatifully written.
Now i can compile every firmware i want, i'm better with ISE.

I discovered many things during these fews days, i really thing that my boad has a counterfeit XC6SLX9. You can find it for 3$ in China maybe less if ordered in quantity. That's why you could have this dev board for less than 20$. So my advice is to avoid this kind of products.
So i decided to create my own design with a genuine XC6SLX9-2TQG144C, totally open source to make my experimentations with MCU. It's a really simple board with simple specifications : 100x100mm 2 layers, 72 I/O on 3 connectors (mesa daughter compatible) with 3x FST16211, a SPI interface and a 16Mbit flash.
Since i'm not familiar with FPGA i'll need your help to correct my mistakes.

After reading the FST16211 datasheet i think I inverted I/O, how can i drive enable pins too ?
Do i have to protect the SPI too ? Maybe with a 8bits TTL like the FST16211 ?
And many other questions like what's the use of these pins :
_ pin 37
_ pin 59
_ pin 60
_ pin 69
_ pin 67
_ pin 73
_ pin 144
Attachments:
Last edit: 02 May 2019 09:34 by gtt38.

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02 May 2019 09:26 #132500 by InMyDarkestHour

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02 May 2019 09:38 #132501 by gtt38
Thank you
I already checked these schematics like many other XC6SLX9 dev boards but it's not helping for this specific use.

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02 May 2019 10:50 #132509 by InMyDarkestHour
The following user(s) said Thank You: gtt38

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02 May 2019 13:32 - 02 May 2019 13:33 #132535 by gtt38
A little bit thank you. I will follow the same specifications as my dev board for these pins.
I will need advices for the 50mhz crystal too
Last edit: 02 May 2019 13:33 by gtt38.

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03 May 2019 01:57 #132590 by InMyDarkestHour
I think you will have to read the Xilinx docs.....especially UG393 regarding PCB design, there's quite a few docs to go through.

Not as straight forward as designing for a simple adruino type project. Keep going you have an interesting project going on.

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