Configuration 7i92 and 7i77 - get error

To 7i92 written 7i77x2D.bit file.
I have configured in PncConf 7i92M and 7i77 board.

And I have problem with first start after configuration.
I get error
I add hal and ini files

What problem could be?
1) I suspect: I made configuration for 2 7i77 boards but run only one board.
2) My PC is "industrial" and has 2 ethernet interfaces, I add also their configuration:

3) PncConf creates wrong configuration for 2.8.1 board, but previously I made configuration for 5i25 boards and doesn't have such problem.

If I run "ip link show", I get such result as in ip.txt file

aleksamc wrote:

To 7i92 written 7i77x2D.bit file.
I have configured in PncConf 7i92M and 7i77 board.

And I have problem with first start after configuration.
I get error

my_cnc.hal:22: parameter ot pin 'hm2_7i92.0.stepgen.timer-number' not found

For starters, delete or comment out the two lines below near the top of your hal file.

setp hm2_7i92.0.dpll.01.timer-us -50
setp hm2_7i92.0.stepgen.timer-number 1

Looks like a pncconf bug

For a 7I77 you probably want:

setp hm2_7i92.0.dpll.01.timer-us -50
setp hm2_7i92.0.encoder.timer-number 1

PCW wrote:

Looks like a pncconf bug

For a 7I77 you probably want:

setp hm2_7i92.0.dpll.01.timer-us -50
setp hm2_7i92.0.encoder.timer-number 1

Get errors when I do that with a 7i77

You need to have the DPLL in the FPGA configuration, 7I92_7i77x2D should have it

PCW wrote:

You need to have the DPLL in the FPGA configuration, 7I92_7i77x2D should have it

I am running 7i92_7i77_7i74D firmware

Whats the relevance of this line?

hm2_7i92.0.encoder.timer-number 1

Would this create encoder timing issues?

Just loaded 7i92_7i77_7i74D firmware and I get:

7 s32 IN -1 hm2_7i92.0.encoder.timer-number

What LinuxCNC version are you running?

Michael wrote:

Whats the relevance of this line?

hm2_7i92.0.encoder.timer-number 1

setp hm2_7i92.0.dpll.01.timer-us -50
setp hm2_7i92.0.encoder.timer-number 1

Will enable DPLL sampling of the encoder position
rather than raw sampling. This reduces the sampling
jitter from as much as a few hundred usec to 250 ns
or so.

The first statement sets DPLL timer 1's sample
time to 50 usec _before_ the nominal read time.
The next statement tells the encoder hardware
to use DPLL encoder sampling rather than
raw sampling (the default timer number of -1
selects raw sampling)

I am 99% sure I also don't have that and have been # out setp hm2_7i92.0.stepgen.timer-number 1 since it was creating errors. That could explain my 5ms delay from encoder response, or part of it.