Configuration 7i92 and 7i77 - get error

bevins
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29 Jan 2021 12:15 #197047 by bevins

Replied by bevins on topic Configuration 7i92 and 7i77 - get error

PCW wrote:
Just loaded 7i92_7i77_7i74D firmware and I get:

7 s32 IN -1 hm2_7i92.0.encoder.timer-number

What LinuxCNC version are you running?

I am running 2.8.1-44

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bevins
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29 Jan 2021 12:25 #197049 by bevins

Replied by bevins on topic Configuration 7i92 and 7i77 - get error

bevins wrote:

PCW wrote:
Just loaded 7i92_7i77_7i74D firmware and I get:

7 s32 IN -1 hm2_7i92.0.encoder.timer-number

What LinuxCNC version are you running?

I am running 2.8.1-44

Pin List for encoders:

Warning: Spoiler!

26  s32   OUT             0  hm2_7i92.0.encoder.00.count
    26  s32   OUT             0  hm2_7i92.0.encoder.00.count-latched
    26  bit   I/O         FALSE  hm2_7i92.0.encoder.00.index-enable <=> x-index-enable
    26  bit   OUT         FALSE  hm2_7i92.0.encoder.00.input-a
    26  bit   OUT         FALSE  hm2_7i92.0.encoder.00.input-b
    26  bit   OUT          TRUE  hm2_7i92.0.encoder.00.input-index
    26  bit   IN          FALSE  hm2_7i92.0.encoder.00.latch-enable
    26  bit   IN          FALSE  hm2_7i92.0.encoder.00.latch-polarity
    26  float OUT             0  hm2_7i92.0.encoder.00.position ==> x-pos-fb
    26  float OUT             0  hm2_7i92.0.encoder.00.position-latched
    26  bit   OUT         FALSE  hm2_7i92.0.encoder.00.quad-error
    26  bit   IN          FALSE  hm2_7i92.0.encoder.00.quad-error-enable
    26  s32   OUT             0  hm2_7i92.0.encoder.00.rawcounts ==> x-pos-rawcounts
    26  s32   OUT             0  hm2_7i92.0.encoder.00.rawlatch
    26  bit   IN          FALSE  hm2_7i92.0.encoder.00.reset
    26  float OUT             0  hm2_7i92.0.encoder.00.velocity ==> x-vel-fb
    26  float OUT             0  hm2_7i92.0.encoder.00.velocity-rpm
    26  s32   OUT             0  hm2_7i92.0.encoder.01.count
    26  s32   OUT             0  hm2_7i92.0.encoder.01.count-latched
    26  bit   I/O         FALSE  hm2_7i92.0.encoder.01.index-enable <=> y-index-enable
    26  bit   OUT         FALSE  hm2_7i92.0.encoder.01.input-a
    26  bit   OUT         FALSE  hm2_7i92.0.encoder.01.input-b
    26  bit   OUT          TRUE  hm2_7i92.0.encoder.01.input-index
    26  bit   IN          FALSE  hm2_7i92.0.encoder.01.latch-enable
    26  bit   IN          FALSE  hm2_7i92.0.encoder.01.latch-polarity
    26  float OUT             0  hm2_7i92.0.encoder.01.position ==> y-pos-fb
    26  float OUT             0  hm2_7i92.0.encoder.01.position-latched
    26  bit   OUT         FALSE  hm2_7i92.0.encoder.01.quad-error
    26  bit   IN          FALSE  hm2_7i92.0.encoder.01.quad-error-enable
    26  s32   OUT             0  hm2_7i92.0.encoder.01.rawcounts ==> y-pos-rawcounts
    26  s32   OUT             0  hm2_7i92.0.encoder.01.rawlatch
    26  bit   IN          FALSE  hm2_7i92.0.encoder.01.reset
    26  float OUT             0  hm2_7i92.0.encoder.01.velocity ==> y-vel-fb
    26  float OUT             0  hm2_7i92.0.encoder.01.velocity-rpm
    26  s32   OUT             0  hm2_7i92.0.encoder.02.count
    26  s32   OUT             0  hm2_7i92.0.encoder.02.count-latched
    26  bit   I/O         FALSE  hm2_7i92.0.encoder.02.index-enable <=> z-index-enable
    26  bit   OUT         FALSE  hm2_7i92.0.encoder.02.input-a
    26  bit   OUT         FALSE  hm2_7i92.0.encoder.02.input-b
    26  bit   OUT          TRUE  hm2_7i92.0.encoder.02.input-index
    26  bit   IN          FALSE  hm2_7i92.0.encoder.02.latch-enable
    26  bit   IN          FALSE  hm2_7i92.0.encoder.02.latch-polarity
    26  float OUT             0  hm2_7i92.0.encoder.02.position ==> z-pos-fb
    26  float OUT             0  hm2_7i92.0.encoder.02.position-latched
    26  bit   OUT         FALSE  hm2_7i92.0.encoder.02.quad-error
    26  bit   IN          FALSE  hm2_7i92.0.encoder.02.quad-error-enable
    26  s32   OUT             0  hm2_7i92.0.encoder.02.rawcounts ==> z-pos-rawcounts
    26  s32   OUT             0  hm2_7i92.0.encoder.02.rawlatch
    26  bit   IN          FALSE  hm2_7i92.0.encoder.02.reset
    26  float OUT             0  hm2_7i92.0.encoder.02.velocity ==> z-vel-fb
    26  float OUT             0  hm2_7i92.0.encoder.02.velocity-rpm
    26  s32   OUT             0  hm2_7i92.0.encoder.03.count
    26  s32   OUT             0  hm2_7i92.0.encoder.03.count-latched
    26  bit   I/O         FALSE  hm2_7i92.0.encoder.03.index-enable
    26  bit   OUT         FALSE  hm2_7i92.0.encoder.03.input-a
    26  bit   OUT          TRUE  hm2_7i92.0.encoder.03.input-b
    26  bit   OUT         FALSE  hm2_7i92.0.encoder.03.input-index
    26  bit   IN          FALSE  hm2_7i92.0.encoder.03.latch-enable
    26  bit   IN          FALSE  hm2_7i92.0.encoder.03.latch-polarity
    26  float OUT             0  hm2_7i92.0.encoder.03.position
    26  float OUT             0  hm2_7i92.0.encoder.03.position-latched
    26  bit   OUT         FALSE  hm2_7i92.0.encoder.03.quad-error
    26  bit   IN          FALSE  hm2_7i92.0.encoder.03.quad-error-enable
    26  s32   OUT         65535  hm2_7i92.0.encoder.03.rawcounts
    26  s32   OUT         65535  hm2_7i92.0.encoder.03.rawlatch
    26  bit   IN          FALSE  hm2_7i92.0.encoder.03.reset
    26  float OUT             0  hm2_7i92.0.encoder.03.velocity
    26  float OUT             0  hm2_7i92.0.encoder.03.velocity-rpm
    26  s32   OUT             0  hm2_7i92.0.encoder.04.count
    26  s32   OUT             0  hm2_7i92.0.encoder.04.count-latched
    26  bit   I/O         FALSE  hm2_7i92.0.encoder.04.index-enable
    26  bit   OUT         FALSE  hm2_7i92.0.encoder.04.input-a
    26  bit   OUT          TRUE  hm2_7i92.0.encoder.04.input-b
    26  bit   OUT          TRUE  hm2_7i92.0.encoder.04.input-index
    26  bit   IN          FALSE  hm2_7i92.0.encoder.04.latch-enable
    26  bit   IN          FALSE  hm2_7i92.0.encoder.04.latch-polarity
    26  float OUT             0  hm2_7i92.0.encoder.04.position
    26  float OUT             0  hm2_7i92.0.encoder.04.position-latched
    26  bit   OUT         FALSE  hm2_7i92.0.encoder.04.quad-error
    26  bit   IN          FALSE  hm2_7i92.0.encoder.04.quad-error-enable
    26  s32   OUT         65535  hm2_7i92.0.encoder.04.rawcounts
    26  s32   OUT         65535  hm2_7i92.0.encoder.04.rawlatch
    26  bit   IN          FALSE  hm2_7i92.0.encoder.04.reset
    26  float OUT             0  hm2_7i92.0.encoder.04.velocity
    26  float OUT             0  hm2_7i92.0.encoder.04.velocity-rpm
    26  s32   OUT             0  hm2_7i92.0.encoder.05.count
    26  s32   OUT             0  hm2_7i92.0.encoder.05.count-latched
    26  bit   I/O         FALSE  hm2_7i92.0.encoder.05.index-enable
    26  bit   OUT         FALSE  hm2_7i92.0.encoder.05.input-a
    26  bit   OUT         FALSE  hm2_7i92.0.encoder.05.input-b
    26  bit   OUT          TRUE  hm2_7i92.0.encoder.05.input-index
    26  bit   IN          FALSE  hm2_7i92.0.encoder.05.latch-enable
    26  bit   IN          FALSE  hm2_7i92.0.encoder.05.latch-polarity
    26  float OUT             0  hm2_7i92.0.encoder.05.position
    26  float OUT             0  hm2_7i92.0.encoder.05.position-latched
    26  bit   OUT         FALSE  hm2_7i92.0.encoder.05.quad-error
    26  bit   IN          FALSE  hm2_7i92.0.encoder.05.quad-error-enable
    26  s32   OUT             0  hm2_7i92.0.encoder.05.rawcounts
    26  s32   OUT             0  hm2_7i92.0.encoder.05.rawlatch
    26  bit   IN          FALSE  hm2_7i92.0.encoder.05.reset
    26  float OUT             0  hm2_7i92.0.encoder.05.velocity
    26  float OUT             0  hm2_7i92.0.encoder.05.velocity-rpm
    26  bit   IN          FALSE  hm2_7i92.0.encoder.hires-timestamp
    26  u32   IN     0x007F2815  hm2_7i92.0.encoder.muxed-sample-frequency
    26  bit   OUT          TRUE  hm2_7i92.0.gpio.000.in

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PCW
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29 Jan 2021 17:15 #197075 by PCW

Replied by PCW on topic Configuration 7i92 and 7i77 - get error

I suspect you are using non-dpll firmware

what does:

mesaflash --device 7i92 --addr 10.10.10.10 -- readhmid

report?

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PCW
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29 Jan 2021 17:34 - 29 Jan 2021 17:35 #197080 by PCW

Replied by PCW on topic Configuration 7i92 and 7i77 - get error

Michael wrote:
I am 99% sure I also don't have that and have been # out setp hm2_7i92.0.stepgen.timer-number 1 since it was creating errors. That could explain my 5ms delay from encoder response, or part of it.

No, adding DPLL retiming will make the average delay between reading the encoders and writing the analog out
slightly longer (by 50 usec in the example)

It's expected that "setp hm2_7i92.0.stepgen.timer-number 1" would cause an error if you
dont have any step generators in your configuration. This is presumably a pncconf bug.

Last edit: 29 Jan 2021 17:35 by PCW.

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bevins
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29 Jan 2021 17:46 - 29 Jan 2021 17:48 #197082 by bevins

Replied by bevins on topic Configuration 7i92 and 7i77 - get error

PCW wrote:
I suspect you are using non-dpll firmware

what does:

mesaflash --device 7i92 --addr 10.10.10.10 -- readhmid

report?

DPLL module is there

Warning: Spoiler!

Configuration Name: HOSTMOT2

General configuration information:

  BoardName : MESA7I92
  FPGA Size: 9 KGates
  FPGA Pins: 144
  Number of IO Ports: 2
  Width of one I/O port: 17
  Clock Low frequency: 100.0000 MHz
  Clock High frequency: 200.0000 MHz
  IDROM Type: 3
  Instance Stride 0: 4
  Instance Stride 1: 64
  Register Stride 0: 256
  Register Stride 1: 256

Modules in configuration:

  Module: DPLL
  There are 1 of DPLL in configuration
  Version: 0
  Registers: 7
  BaseAddress: 7000
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: WatchDog
  There are 1 of WatchDog in configuration
  Version: 0
  Registers: 3
  BaseAddress: 0C00
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: IOPort
  There are 2 of IOPort in configuration
  Version: 0
  Registers: 5
  BaseAddress: 1000
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: MuxedQCount
  There are 6 of MuxedQCount in configuration
  Version: 3
  Registers: 5
  BaseAddress: 3600
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: MuxedQCountSel
  There are 1 of MuxedQCountSel in configuration
  Version: 0
  Registers: 0
  BaseAddress: 0000
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: SSerial
  There are 2 of SSerial in configuration
  Version: 0
  Registers: 6
  BaseAddress: 5B00
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 64 bytes

  Module: LED
  There are 1 of LED in configuration
  Version: 0
  Registers: 1
  BaseAddress: 0200
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

Configuration pin-out:

IO Connections for P2
Pin#                  I/O   Pri. func    Sec. func       Chan      Pin func        Pin Dir

 1                      0   IOPort       SSerial          0        TXEn2           (Out)
14                      1   IOPort       SSerial          0        TXData2         (Out)
 2                      2   IOPort       SSerial          0        RXData2         (In)
15                      3   IOPort       SSerial          0        TXData1         (Out)
 3                      4   IOPort       SSerial          0        RXData1         (In)
16                      5   IOPort       SSerial          0        TXData0         (Out)
 4                      6   IOPort       SSerial          0        RXData0         (In)
17                      7   IOPort       MuxedQCountSel   0        MuxSel0         (Out)
 5                      8   IOPort       MuxedQCount      0        MuxQ-A          (In)
 6                      9   IOPort       MuxedQCount      0        MuxQ-B          (In)
 7                     10   IOPort       MuxedQCount      0        MuxQ-IDX        (In)
 8                     11   IOPort       MuxedQCount      1        MuxQ-A          (In)
 9                     12   IOPort       MuxedQCount      1        MuxQ-B          (In)
10                     13   IOPort       MuxedQCount      1        MuxQ-IDX        (In)
11                     14   IOPort       MuxedQCount      2        MuxQ-A          (In)
12                     15   IOPort       MuxedQCount      2        MuxQ-B          (In)
13                     16   IOPort       MuxedQCount      2        MuxQ-IDX        (In)

IO Connections for P1
Pin#                  I/O   Pri. func    Sec. func       Chan      Pin func        Pin Dir

 1                     17   IOPort       SSerial          1        RXData0         (In)
14                     18   IOPort       SSerial          1        RXData1         (In)
 2                     19   IOPort       SSerial          1        RXData2         (In)
15                     20   IOPort       SSerial          1        RXData3         (In)
 3                     21   IOPort       SSerial          1        TXData0         (Out)
16                     22   IOPort       SSerial          1        TXData1         (Out)
 4                     23   IOPort       SSerial          1        TXData2         (Out)
17                     24   IOPort       SSerial          1        TXData3         (Out)
 5                     25   IOPort       SSerial          1        RXData4         (In)
 6                     26   IOPort       SSerial          1        RXData5         (In)
 7                     27   IOPort       None           
 8                     28   IOPort       None           
 9                     29   IOPort       SSerial          1        TXData4         (Out)
10                     30   IOPort       SSerial          1        TXData5         (Out)
11                     31   IOPort       None           
12                     32   IOPort       None           
13                     33   IOPort       None

Last edit: 29 Jan 2021 17:48 by bevins.

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PCW
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29 Jan 2021 21:25 #197091 by PCW

Replied by PCW on topic Configuration 7i92 and 7i77 - get error

OK well that's fairly mysterious, I just built 2.8.1 and the pin is there:

7 s32 IN -1 hm2_7i92.0.encoder.timer-number

I had been checking with master but 2.8.1 works for me

Can you check the bitfile checksum?

$ md5sum 7i92_7i77_7i74D.bit
9adaf5281f07f798d9fa87580f63e6c2 7i92_7i77_7i74D.bit

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bevins
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29 Jan 2021 22:19 - 29 Jan 2021 22:19 #197095 by bevins

Replied by bevins on topic Configuration 7i92 and 7i77 - get error

PCW wrote:
OK well that's fairly mysterious, I just built 2.8.1 and the pin is there:

7 s32 IN -1 hm2_7i92.0.encoder.timer-number

I had been checking with master but 2.8.1 works for me

Can you check the bitfile checksum?

$ md5sum 7i92_7i77_7i74D.bit
9adaf5281f07f798d9fa87580f63e6c2 7i92_7i77_7i74D.bit

Ill check it after supper but i got the 7i92 zip file from freeby.mesanet site. I compiled mesaflash from github and got the 7i92.zip from your site.

Maybe the zip file dont have the correct files in it? Can you send the bit and pin files?

Last edit: 29 Jan 2021 22:19 by bevins.

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bevins
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29 Jan 2021 22:35 #197096 by bevins

Replied by bevins on topic Configuration 7i92 and 7i77 - get error

Thats bizarre. The checksum works out.

Is it a config on the loadrt line?

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PCW
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29 Jan 2021 23:01 #197097 by PCW

Replied by PCW on topic Configuration 7i92 and 7i77 - get error

Not unless the config line disabled the DPLL

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aleksamc
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30 Jan 2021 03:18 - 30 Jan 2021 03:20 #197110 by aleksamc

Replied by aleksamc on topic Configuration 7i92 and 7i77 - get error

I changed stepgen to encoder:

hm2_7i92.0.encoder.timer-number

and graphical interface starts.

But I get another error:

hm2_7i92.9: Watchdog has bit! (set the has-bit to False to resume)
hm2_7i92.0: Error after doit clean

I use Intel J1900 fanless PC.

In BIOS I previously disablem all parameters that could make delay and also made isolcpu=2,3 that gives me very good latency (10k to 15k).

Last edit: 30 Jan 2021 03:20 by aleksamc.

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