New project, litehm2: a hostmot2 port to linsn rv901t

Might be this:
(from the 7I92 manual)

The configuration utilities expect standard FPGA bitfiles without any multiboot features
enabled. If multiboot FPGA files are loaded they will likely cause a configuration failure.

Might also be an issue with the flash chip size detection.
 

hi all.
i have problem.


(litexcnc) vasya@debian:~/litehm2$ make
make -f Makefile.target TARGET=rv901t_4out__3stepgen_2enc_1pwm
make[1]: Entering directory '/home/vasya/litehm2'
dd if=/dev/zero of=build/rv901t_4out__3stepgen_2enc_1pwm/firmware/firmware.bin bs=32k count=1
1+0 records in
1+0 records out
32768 bytes (33 kB, 32 KiB) copied, 0.00169724 s, 19.3 MB/s
dd if=/dev/zero of=build/rv901t_4out__3stepgen_2enc_1pwm/firmware/loader.bin bs=4k count=1
1+0 records in
1+0 records out
4096 bytes (4.1 kB, 4.0 KiB) copied, 0.000610246 s, 6.7 MB/s
./litehm2.py --builddir=build/rv901t_4out__3stepgen_2enc_1pwm --config=configs/rv901t_4out__3stepgen_2enc_1pwm.conf
INFO:S6PLL:Creating S6PLL, speedgrade -2.
INFO:S6PLL:Registering Single Ended ClkIn of 25.00MHz.
INFO:S6PLL:Creating ClkOut0 sys of 80.00MHz (+-10000.00ppm).
INFO:S6PLL:Creating ClkOut1 fast of 200.00MHz (+-10000.00ppm).
Traceback (most recent call last):
  File "/home/vasya/litehm2/./litehm2.py", line 201, in <module>
    main()
  File "/home/vasya/litehm2/./litehm2.py", line 194, in main
    soc = LiteHM2(ip_address=args.ip_address,
          ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/home/vasya/litehm2/./litehm2.py", line 94, in __init__
    main_ram_init = get_mem_data(builddir + "/firmware/firmware.bin",
                    ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
TypeError: get_mem_data() got an unexpected keyword argument 'data_width'
make[1]: *** [Makefile.target:10: litehm2] Error 1
make[1]: Leaving directory '/home/vasya/litehm2'
make: *** [Makefile:8: bitstreams/rv901t_4out__3stepgen_2enc_1pwm.bit] Error 2
(litexcnc) vasya@debian:~/litehm2$ 

 

Hello, sir
The PWM circuit board of hm2_lite has only two pins: pwm.x.out and pwm.x.dir.
Can it be used to control the forward and reverse rotation of the servo motor and run in speed mode by analog voltage? With an encoder, can the xyz axis be controlled by pid?

There are at least three ways to generate a bipolar analog voltage from PWM


1. Using PWM/DIR (typically using an op-amp circuit that
is changed from inverting to non-inverting by a analog switch)
(this has the disadvantage of a glitch when direction changes)

2. Using the PWM generators UP/DOWN mode and summing
a positive and negative filtered voltage.
(this has the disadvantage that the filter time constant
varies with the input)

3. Using the PWM generators offset mode (so 0 = 50%) and an op-amp
filter that has a DC offset of - full scale
(This has the disadvantage that you lose 1 bit of resolution, which may not matter
if you use dithering)

Thank you for your answer. Wish you good luck

I didn't have a programmer at hand and found a very cheap option xilinx virtual cable. 
It flashes perfectly. You just need to solder another contact to the ground on the board.
TDI = 4, TDO = 5, TCK = 6, TMS = 7, GND
Author's page where you can download gitee.com/xiaowuzxc/ESP32-XVC
"Over-the-air" programming over ESP32-C3
For IMPACT ise configuration JTAG spartan 6 xc6slx16
Can also configure for programming in flash memory in impact
Your host can find out from any program for scanning the ip environment.On my phone WOM WIFI
For example IMPACT
xilinx_xvc host=host=192.168.0.103:2542 disableversioncheck=true

If there is no ISE Xilinx there is a standalone programmer openFPGALoader
For openFPGALoader configuration spartan 6 xc6slx16
Write-flash JTAG to SPI bridge  -f

sudo openFPGALoader -c xvc-client --ip <your ip> --port 2542 --fpga-part xc6slx16 -f <your bit file>

Write-sram JTAG  -m
sudo openFPGALoader -c xvc-client --ip <your ip> --port 2542 --fpga-part xc6slx16 -m <your bit file>

For example

sudo openFPGALoader -c xvc-client --ip 192.168.0.103 --port 2542 --fpga-part xc6slx16 -f rv901t_4out__3stepgen_2enc_1pwm.bit
sudo openFPGALoader -c xvc-client --ip 192.168.0.103 --port 2542 --fpga-part xc6slx16 -m rv901t_4out__3stepgen_2enc_1pwm.bit

/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

sudo apt install git gzip libftdi1-2 libftdi1-dev libhidapi-dev libudev-dev zlib1g-dev cmake pkg-config make g++
  
git clone github.com/trabucayre/openFPGALoader
cd openFPGALoader
mkdir build
cd build
cmake .. 
cmake --build .
sudo make install