connecting DIY glue logic to linuxCNC through HAL

Unfortunately you have a NetMOS/MOSChip parallel port chip.
These chips (98xx series) do not implement EPP mode correctly

Hi PCW,

I am using the 99xx chipset, not the 98xx, but however I just found this text in the web:

Q0009: Can I manually force MCS99xx parallel port at a specific LPT mode (such as EPP, ECP, etc.)?

A0009: Only the MCS99xx DOS and Windows NT drivers have a mechanism to manually select the desired LPT
Mode for MCS99xx Parallel port. The Windows systems are supposed to be able to auto-switch to a proper
LPT mode for PCIe based parallel port devices. Unfortunately, this LPT mode automatic switching
functionality does not work very well with PCIe based Parallel port devices on Windows systems. MCS99xx
can support SPP and PS/2 Modes without any problems. The EPP and ECP modes supporting varies from machine
to machine and depends on the Operating System being used. Both EPP and ECP modes require two banks of
Standard/Extended registers to control the standard/enhanced functionality of MCS99xx Parallel port.
The base address of 2nd bank Extended registers must be equal to "the base address of 1st bank Standard
registers + 400h" to meet the IEEE-1284 standard specification. Unfortunately, the PCIe specification
does not make any guarantees that two resource requests will have any specific relationship to each other.
We request the two banks with the desired offset, but the system does not always honor those requests,
and often returns the extended register bank at some entirely different address than what we requested.
When this occurs, neither EPP nor ECP Mode will be workable. For this reason, some software (including
Device Drivers for Printers etc.) will not work with MCS99xx PCIe based Parallel port.

If I understand this on the right way, it means, that the PCIe is the problem ... but my computer has only USB and one PCIe-Slot.

Sooo, even if it is slower to set the read/write bit by software, it is maybe the only way to get it work.

I get a speed of over 450k Bytes/sec with the trick to controle the direction by software. I am going to use this way for now.

Thanks for your help,
bye,
Plasturo

PS.: If there is somebody who can tell me how to bring this card by software into EPP mode, I will be very happy. Maybe there is a way to get the address of the high rigister bank, maybe it is the second address of the lspci -vv info?

For the NetMOS PCI cards the problem is unfixable
(bad hardware that does not implement EPP correctly)

So I would not assume its a software setup issue. The PCI cards have the expected
registers in the standard places, but it doesn't help because the hardware is broken

I am not familiar with the PCIE cards but I would suspect them of the same poor hardware design

If you want to test working EPP hardware, motherboard hardware almost always works,
and avoid NetMOS/MOSChip like the plague...

plasturo wrote:

PS.: If there is somebody who can tell me how to bring this card by software into EPP mode, I will be very happy. Maybe there is a way to get the address of the high rigister bank, maybe it is the second address of the lspci -vv info?

I have a program that will set a standard motherboard port to EPP mode. But, many of the newer
ports don't use the old offset of 0x402 between the data port address and the ECR register.
Your ECR register is probably at 0xE012 (but possibly could be 0xE002). it will generally be in
the OTHER address group from the one with the data port register.

My program is at pico-systems.com/codes/pcisetup.tgz

You can unpack it with tar xzvf pcisetup.tgz

and it needs to be run with sudo priveledges as it affects device registers.
It automatically addrs the 0x402, so you have to compensate for that.
So, if you ran it with this command :

sudo ./pcisetup dc10
I think it would perform the operation on I/O address e012.

Jon

plasturo wrote:

The base address of 2nd bank Extended registers must be equal to "the base address of 1st bank Standard
registers + 400h" to meet the IEEE-1284 standard specification.

My understanding is this offset of 400h between the port registers and the extended control
regisers has NOTHING to do with IEEE-1284, but comes from an ancient MicroSoft
document about the register layout for multi-IO chips that were the rage in motherboartd
designs in the 386 and early 486 days. IEEE-1284 is a very loose definition of signalling
protocol on the cable and parallel port connectors, and doesn't define the register
layout on the PC at all.

Jon

@PCW:
Yes, when I bought the card, there was the text in the web catalogue saying it is EPP-Mode included ...but it is not. But which card can I use instead?

@jmelson:
Thanks for the program, I will try it next weekend, now, I have to stop the handicraft work.

Bye,
Plasturo

Its certainly worth a try to poke at the upper register set to see if the card can be set in EPP mode
MOSChip has data sheets available if you register (I have an old 9901 data sheet but it has zero information on
parallel port mode setup)

Yeah, it works additionally with a small halrun-programm it is running now.
(siggen + thread + stepgen + own-driver)
I changed the Address Latch to two 74xx163. Now I can write addresses
plus counting the address up after every datawritecircle. That makes the
transfer quicker.
Here a picture of the hardware

The next step is to programm and connect the amplifier of the stepper,
here a picture of one (I build four until now)