Another Newbie with PCIE parallel port problems
27 Mar 2019 00:21 - 27 Mar 2019 00:23 #129741
by cmelojr
Replied by cmelojr on topic Another Newbie with PCIE parallel port problems
Tested my parallel cable and that was good.
Ran uname -a and got this:
Linux LinuxCNC 3.4-9-rtai-686-pae #1 SMP PREEMPT Debian 3.4.55-4linuxcnc i686 GNU/Linux
Assuming the rtai is the real time kernel.
Jumped pin 2 two ground and ran ptest. I'm assuming that I must edit the following line: loadrt hal_parport cfg="0x378 out"
I tried 0xc000 and 0xc010 on that line with the pin 2 jumped to ground and hit the pin 2 button. Should I expect something?
Ran uname -a and got this:
Linux LinuxCNC 3.4-9-rtai-686-pae #1 SMP PREEMPT Debian 3.4.55-4linuxcnc i686 GNU/Linux
Assuming the rtai is the real time kernel.
Jumped pin 2 two ground and ran ptest. I'm assuming that I must edit the following line: loadrt hal_parport cfg="0x378 out"
I tried 0xc000 and 0xc010 on that line with the pin 2 jumped to ground and hit the pin 2 button. Should I expect something?
Last edit: 27 Mar 2019 00:23 by cmelojr.
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27 Mar 2019 00:23 #129743
by cmelojr
Replied by cmelojr on topic Another Newbie with PCIE parallel port problems
If I run sudo lspci -v then the ports show up as disabled. Attached my output. I tried running the series of commands again but this time with the same result of them showing up as disabled still.
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27 Mar 2019 03:33 #129747
by tommylight
Replied by tommylight on topic Another Newbie with PCIE parallel port problems
Pin 2 to pin 10.
Pin 10 or 11 or 12 or 13 or 15 to ground.
Not pin 2 to ground
Pin 10 or 11 or 12 or 13 or 15 to ground.
Not pin 2 to ground
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28 Mar 2019 01:14 #129812
by andypugh
Googling for that line of the output gave me this link:
forum.linuxcnc.org/49-basic-configuratio...rralel-port-disabled
Have you checked to see if the slot or port is disabled in the BIOS?
Replied by andypugh on topic Another Newbie with PCIE parallel port problems
If I run sudo lspci -v then the ports show up as disabled.
Googling for that line of the output gave me this link:
forum.linuxcnc.org/49-basic-configuratio...rralel-port-disabled
Have you checked to see if the slot or port is disabled in the BIOS?
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- Richard J Kinch
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28 Mar 2019 07:20 - 29 Mar 2019 03:22 #129819
by Richard J Kinch
Here's my success report with the same PCIe card (SYBA SD-PEX10005 board product incorporating the ASIX MCS9900 chip, which is an "PCIe to Multi I/O(4S, 2S+1P) Controller" according to the Product Brief ). It worked on the first try, so perhaps my notes will help you find some difference with your observations. This was tested on a fresh, plain install of LinuxCNC 2.7.14 from the current live/install image. After the plain install, the only modifications I made to the LinuxCNC configuration was to copy and configure (for I/O address) the ptest works as shown below.
I installed the card (which I happened to have purchased from the same Amazon link as in your original post) into my ASRock Q1900B-ITX motherboard (has been successful in LinuxCNC application with just its one onboard parallel port that shows up at 0x378). The BIOS still configures the onboard port, but nothing shows up in the BIOS configuration for the PCIe gadgets.
Another qualification on this board tested: what I received from Amazon 03/2019 was not the type shown in the listing photo or on sybausa.com photos as the model SD-PEX10005. Those photos show a diagonally mounted chip, whereas what I received was a layout where everything is rectangular. I suspect that the rectangular version is a later build (which ought to have a distinctive model number, but doesn't), and is actually a reduction of the SD-PEX50030 (which is a board that has the serial port off-chip support components and comes with a 2nd bracket with a pair of DE-9P connectors to connect to them) with the serial port parts not populated. The rectangular board has an indicia "EM9900-I2(100720) MADE IN CHINA" on the back traces. Given that Taiwan (ASIX), China, India (MosChip), and Syba (California importer) have a hand in this product, it's no surprise that the critical engineering details are poorly documented and controlled, but that's the situation with support for the vintage parallel port concept. Another puzzle is that the upper right of the board has an unpopulated DC-DC converter circuit, which I assume is what generates the +/- voltages for RS-232C. The MosChip chip provides all the signals as 3.3V GPIO levels, and the support circuits have to shift this to RS-232C. The parallel port signals appear to be directly connected to the GPIO signals and levels. This suggests that all the serial port signals and GPIO pins are available on the board, at 3.3V GPIO levels; perhaps these could be wired out to harvest another dozen signal pins out of the board beyond the parallel port set.
I guessed the address needed for HAL as 0xe010 as shown in the "sudo lspci -vv" output which was:
Based on this output reporting "I/O ports at e010", I edited the
ptest configuration
ptest.hal as follows:
With ptest running, a voltmeter across ground and any given output pin would read 0.7mV (button off) and 3.3V (button pressed) when pressing the ptest output buttons, and shorting the input pins with a 470ohm resistor to ground would switch the ptest pin display from on (when open) to off (when shorted).
This hardware (motherboard with parallel port, power supply, 4GB DDR3, 1U rackmount case, 2nd parallel port PCIe) costs about $250 to assemble new, plus whatever hard drive you want to use. It all fits decently in the 1U format. I would suggest this street price is an upper bound to what you can potentially save by rummaging and struggling with an existing system.
Replied by Richard J Kinch on topic Another Newbie with PCIE parallel port problems
If I run sudo lspci -v then the ports show up as disabled.
Here's my success report with the same PCIe card (SYBA SD-PEX10005 board product incorporating the ASIX MCS9900 chip, which is an "PCIe to Multi I/O(4S, 2S+1P) Controller" according to the Product Brief ). It worked on the first try, so perhaps my notes will help you find some difference with your observations. This was tested on a fresh, plain install of LinuxCNC 2.7.14 from the current live/install image. After the plain install, the only modifications I made to the LinuxCNC configuration was to copy and configure (for I/O address) the ptest works as shown below.
I installed the card (which I happened to have purchased from the same Amazon link as in your original post) into my ASRock Q1900B-ITX motherboard (has been successful in LinuxCNC application with just its one onboard parallel port that shows up at 0x378). The BIOS still configures the onboard port, but nothing shows up in the BIOS configuration for the PCIe gadgets.
Another qualification on this board tested: what I received from Amazon 03/2019 was not the type shown in the listing photo or on sybausa.com photos as the model SD-PEX10005. Those photos show a diagonally mounted chip, whereas what I received was a layout where everything is rectangular. I suspect that the rectangular version is a later build (which ought to have a distinctive model number, but doesn't), and is actually a reduction of the SD-PEX50030 (which is a board that has the serial port off-chip support components and comes with a 2nd bracket with a pair of DE-9P connectors to connect to them) with the serial port parts not populated. The rectangular board has an indicia "EM9900-I2(100720) MADE IN CHINA" on the back traces. Given that Taiwan (ASIX), China, India (MosChip), and Syba (California importer) have a hand in this product, it's no surprise that the critical engineering details are poorly documented and controlled, but that's the situation with support for the vintage parallel port concept. Another puzzle is that the upper right of the board has an unpopulated DC-DC converter circuit, which I assume is what generates the +/- voltages for RS-232C. The MosChip chip provides all the signals as 3.3V GPIO levels, and the support circuits have to shift this to RS-232C. The parallel port signals appear to be directly connected to the GPIO signals and levels. This suggests that all the serial port signals and GPIO pins are available on the board, at 3.3V GPIO levels; perhaps these could be wired out to harvest another dozen signal pins out of the board beyond the parallel port set.
I guessed the address needed for HAL as 0xe010 as shown in the "sudo lspci -vv" output which was:
01:00.0 Parallel controller: NetMos Technology Device 9900 (prog-if 03 [IEEE1284])
Subsystem: Device a000:2000
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 11
Region 0: I/O ports at e010 [size=8]
Region 1: I/O ports at e000 [size=8]
Region 2: Memory at d0701000 (32-bit, non-prefetchable) [size=4K]
Region 5: Memory at d0700000 (32-bit, non-prefetchable) [size=4K]
Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+
Address: 0000000000000000 Data: 0000
Capabilities: [78] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0-,D1-,D2-,D3hot+,D3cold+)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [80] Express (v1) Legacy Endpoint, MSI 00
DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <1us, L1 <2us
ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+
MaxPayload 128 bytes, MaxReadReq 512 bytes
DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend-
LnkCap: Port #1, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <64ns, L1 <1us
ClockPM+ Surprise- LLActRep- BwNot-
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk-
ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt-
Capabilities: [100 v1] Virtual Channel
Caps: LPEVC=0 RefClk=100ns PATEntryBits=1
Arb: Fixed- WRR32- WRR64- WRR128-
Ctrl: ArbSelect=Fixed
Status: InProgress-
VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01
Status: NegoPending- InProgress-
VC1: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
Ctrl: Enable- ID=1 ArbSelect=Fixed TC/VC=00
Status: NegoPending- InProgress-
Capabilities: [800 v1] Advanced Error Reporting
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
CESta: RxErr+ BadTLP- BadDLLP- Rollover+ Timeout+ NonFatalErr+
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-loadrt hal_parport cfg="0xe010 out"
loadusr -Wn PortTest pyvcp -c PortTest ptest.xml
loadrt threads name1=porttest period1=1000000
addf parport.0.read porttest
addf parport.0.write porttest
net pin01 PortTest.btn01 parport.0.pin-01-out PortTest.led-01
net pin02 PortTest.btn02 parport.0.pin-02-out PortTest.led-02
net pin03 PortTest.btn03 parport.0.pin-03-out PortTest.led-03
net pin04 PortTest.btn04 parport.0.pin-04-out PortTest.led-04
net pin05 PortTest.btn05 parport.0.pin-05-out PortTest.led-05
net pin06 PortTest.btn06 parport.0.pin-06-out PortTest.led-06
net pin07 PortTest.btn07 parport.0.pin-07-out PortTest.led-07
net pin08 PortTest.btn08 parport.0.pin-08-out PortTest.led-08
net pin09 PortTest.btn09 parport.0.pin-09-out PortTest.led-09
net pin14 PortTest.btn14 parport.0.pin-14-out PortTest.led-14
net pin16 PortTest.btn16 parport.0.pin-16-out PortTest.led-16
net pin17 PortTest.btn17 parport.0.pin-17-out PortTest.led-17
net pin10 parport.0.pin-10-in PortTest.led-10
net pin11 parport.0.pin-11-in PortTest.led-11
net pin12 parport.0.pin-12-in PortTest.led-12
net pin13 parport.0.pin-13-in PortTest.led-13
net pin15 parport.0.pin-15-in PortTest.led-15
start
# loadusr halmeterWith ptest running, a voltmeter across ground and any given output pin would read 0.7mV (button off) and 3.3V (button pressed) when pressing the ptest output buttons, and shorting the input pins with a 470ohm resistor to ground would switch the ptest pin display from on (when open) to off (when shorted).
This hardware (motherboard with parallel port, power supply, 4GB DDR3, 1U rackmount case, 2nd parallel port PCIe) costs about $250 to assemble new, plus whatever hard drive you want to use. It all fits decently in the 1U format. I would suggest this street price is an upper bound to what you can potentially save by rummaging and struggling with an existing system.
Last edit: 29 Mar 2019 03:22 by Richard J Kinch.
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28 Mar 2019 07:46 #129823
by pl7i92
Replied by pl7i92 on topic Another Newbie with PCIE parallel port problems
on the PCIE there are 2 Parports
as the output shows
Region 0: I/O ports at e010
Region 1: I/O ports at e000
as the output shows
Region 0: I/O ports at e010
Region 1: I/O ports at e000
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28 Mar 2019 08:21 #129828
by InMyDarkestHour
Replied by InMyDarkestHour on topic Another Newbie with PCIE parallel port problems
Lenovo have a habit of "blacklisting hardware"........usually your system wont boot when this happens.
I'd suggest trying some Lenovo support forums. (You may blow their minds if you say you are a linux user...if asked which distro just say debian.
For some reason it appears to be disabling those particular I/O ports.
Have you tried the card in different slots ?
I'd suggest trying some Lenovo support forums. (You may blow their minds if you say you are a linux user...if asked which distro just say debian.
For some reason it appears to be disabling those particular I/O ports.
Have you tried the card in different slots ?
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28 Mar 2019 13:53 #129834
by cmelojr
Replied by cmelojr on topic Another Newbie with PCIE parallel port problems
Wow thanks for all the replies. I haven't had any luck with it yet. The BIOS are no help at all. There's no options to turn on/off that could help/hurt. They're very basic. I bought a different card that should be here tonight. I did read another thread where another user had a similar issue and fixed it by trying another card. I'll report back if it works.
Thanks!
Thanks!
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28 Mar 2019 23:10 #129871
by Richard J Kinch
Incorrect! The ASIX (MosChip) MCS9900CV-AA chip on this board provides at most one physical parallel port, which I found responsive to the address I described earlier. The SYBA board provides the serial port connection features, but the components are not populated on the board so there's no serial port ready to use on the board.
The other I/O port address likely is for the serial ports and six GPIO pins that the chip provides. The I/O port architecture is not documented in the ASIX product literature, but perhaps would be verified somewhere in the Linux driver source code which ASIX provides.
Replied by Richard J Kinch on topic Another Newbie with PCIE parallel port problems
on the PCIE there are 2 Parports
as the output shows
Region 0: I/O ports at e010
Region 1: I/O ports at e000
Incorrect! The ASIX (MosChip) MCS9900CV-AA chip on this board provides at most one physical parallel port, which I found responsive to the address I described earlier. The SYBA board provides the serial port connection features, but the components are not populated on the board so there's no serial port ready to use on the board.
The other I/O port address likely is for the serial ports and six GPIO pins that the chip provides. The I/O port architecture is not documented in the ASIX product literature, but perhaps would be verified somewhere in the Linux driver source code which ASIX provides.
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28 Mar 2019 23:30 #129872
by cmelojr
Replied by cmelojr on topic Another Newbie with PCIE parallel port problems
So as recommended by this thread: forum.linuxcnc.org/49-basic-configuratio...ng-disabled?start=10
I bought the startech board. Already having more success. I was able to edit ptest.hal to the correct address on the board and jump pins 2 & 10 and see a response. Then also activate pin 2 on the screen and see voltage across pin 2 and ground. If I plug the cable into my BOB and hit pin 2 on the screen my stepper motor will try and turn.
After editing the .hal file for my newest stepconfig I still can't get my motor to turn but perhaps that's a problem for another thread or I can figure out on my own. I have a feeling I have a different newbie mistake going on there.
Thanks everyone
I bought the startech board. Already having more success. I was able to edit ptest.hal to the correct address on the board and jump pins 2 & 10 and see a response. Then also activate pin 2 on the screen and see voltage across pin 2 and ground. If I plug the cable into my BOB and hit pin 2 on the screen my stepper motor will try and turn.
After editing the .hal file for my newest stepconfig I still can't get my motor to turn but perhaps that's a problem for another thread or I can figure out on my own. I have a feeling I have a different newbie mistake going on there.
Thanks everyone
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