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That did not take long! ?
This makes it usable with Mesa boards and even parallel ports as they can easily count encoder signals

Normally on a 4 layer card you do not need top or bottom fills
unless for heat sinking or shielding. You do need to be a bit careful 
about the 3.3V/1.2V plane cut/bypass capacitors/supply inductance,
and some under FPGA filling of the VCC plane can help here.

The SPI clock will be the fussiest signal so if you are routing it
a long distance, it may need parallel termination at the end of the trace
(series termination does not work with two endpoints)

thanks i will give this a try tonight.
i did not know ther was a "qtvcp copy" tool
i duplacated the directory and replaced the ui fie and renamed one ot two others.
that obiously did not work.
thanks for your help.