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Note that the pins listed in the source file comments are DB25 pins

so

7I90  P4.1  --> DB25.1
7I90  P4.3  --> DB25.14
7I90  P4.5  --> DB25.2

etc

Thanks a lot for the explanation! I will try this solution.

Hi thanks for your answer. Yes i saw your Macros and i think they look really good. You did and do a great jobs there for all, thank you for that! But as far as i understand them, you can only use one at a time right? and there is also no macro for a free contur ? or do i miss something? 

edit: oh sorry my bad, they are from andypugh of course! so thanks andy

Note that this is not a standard configuration as the 7I90 is a 50 pin connector FPGA card
and the 7I85S is s 25 pin FPGA card daughtercard. I pinned this out so a flat cable adapter
should be relatively simple (look at the included VHD source file for the pinout)

 

This has 3 stepgens and 1 PWMgen, 4 encoders and a sserial port
(on the 7I85S) 
 

Very briefly:

In the hal file (use the sample: basic7i97 or use MesaCT to generate the basic configurations)
The PID output pin connects to the PWM value pin. You would change this connection to 
add the abs component so you have:

PID output --> abs in --> abs out --> PWM value

That is, for example, in the basic7i97 hal file you have:

net x-output     => [HMOT](CARD0).pwmgen.00.value

This would need to change to:

net x-output     => abs.0.in
net abs-x-output    <= abs.0.out
net abs-x-output     => [HMOT](CARD0).pwmgen.00.value