LinuxCNC + Orange Pi

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31 Mar 2021 06:40 - 31 Mar 2021 06:42 #204175 by Bari
Replied by Bari on topic LinuxCNC + Orange Pi
A working Linux image is a good start! :)

Lots of ARISC info here:
linux-sunxi.org/AR100
Last edit: 31 Mar 2021 06:42 by Bari. Reason: added arisc info link

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31 Mar 2021 06:44 - 31 Mar 2021 06:45 #204176 by twoflowers
Replied by twoflowers on topic LinuxCNC + Orange Pi
Here they are ( forum.linuxcnc.org/9-installing-linuxcnc...tools-and-no-systemd - but I think I posted the link to the OrangePi Images somewhere else):
github.com/zwieblum/devuan-images
Last edit: 31 Mar 2021 06:45 by twoflowers.
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06 Apr 2021 06:36 #205039 by tjtr33
Replied by tjtr33 on topic LinuxCNC + Orange Pi
Hi, i've been looking into adding better arisc implementation of arisc_stepgen and arisc_gpio, esp for orange pi.

I have _just_ rediscovered the relevant code in the original John Kasunich (JMK) stepgen code, It's in 'timer1 timer2 timer3'.

The correct rules for step timing are in the man page for stepgen. Most relevant are the definitions of dirsetup and dirhold, and how they can be implemented in code. I made some assumptions that they must begin with falling edge of step signal. Then i found them to be just as sketched on paper.

The relevant bits are in the code for three timers. The technique used avoids a lot of math by assuming the entire time (steplength, dirsetup, dirhold and combinations of those) can be represenedt by part of a 32 bit value. Each timer is a 32 bit accumulator. An increment is calculated for each timer. Every cycle adds one increment to the accumulator. A single high water bit mark is chosen in the accumulator. The high water bit becomes SET when the sum of increments pass it ( whne the time has elapsed). This methiod is easy on the cpu load.
This method is clever but convoluted. It is called a DDS in the code (Direct Digital Synthesis) but dont bother trying to allign the code with the Wikipedia (or other) defintion. The high water mark and sized increment describes it better.
Anyway, discovery of the code and technique is important to enabling similar in the arisc_stegen code.
Understanding the size of the base and servo periods is very important. The worst timin scenario is taking a new step in a different direct than last. You have to hold the step line of steplen nS, and you have to hold the direction line for dirhold nS, and you have to set the new directionline and wait dirsetup time before taking the new step.
If you have a steplen of 5000nx and a dirhold of 20000ns and a dirsetup of 20000, then you can calculate the worse case time with safeperiod = jitter + steplen + dirhold + dirsetup. with RPi or OPi jitter of 50000nS, the safeperiod is 50+5+20+20 = 95uS. not very fast :-( .
that's 10526 steps/sec ( dblstep) or 79mm/sec for my .0075 stepsize
or 39.5mm/sec w/o dblstep (2.3meters/min, ok but pretty slow)

This make the arisc driver appealing because it removes the jitter component of formula.
In arisc ( without jitter), the step rate increases
1sec/45uS=22222step/sec.(with dblstep)
thats 10meters/min at my stepsize of .0075
and 5meter/min without doublstep

I need to use the arisc_gpio code in a loop to see if the arisc (like a co_processor ) is verifiable and suited to realtime ( is really deterministic ).

Also, this means that the arisc 'core' doesnt need to be re-wrtten, only th arisc_stepgen and possibly the arisc_gpio code.

I do need to learn howto build it ( it uses the arisc instruction set),
and learn if it needs any installation in the arisc space.

Bye for now, lots todo.

Hope this is hopeful ;-)
tjtr33
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06 Apr 2021 06:44 #205040 by tjtr33
Replied by tjtr33 on topic LinuxCNC + Orange Pi
Hi Bari
how would you suggest verifying that an Opi arisc bit-toggle-square-wave
was really stabile, not jittering?
Maybe: loop back an output to a input pin with a counter ,
then count a million,
then capture system time,
then divide?
I dont see how a scope would show anything if the error was small
and we want non-existant ( ? true? )

tjtr33

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07 Apr 2021 02:29 #205223 by Bari
Replied by Bari on topic LinuxCNC + Orange Pi
Tjtr33,

Depends on your scope

But yeah like we do the latency jitter histogram test for base periods only for a ARISC generated clock.

github.com/LinuxCNC/linuxcnc/blob/master...ts/latency-histogram

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08 Apr 2021 12:17 - 08 Apr 2021 15:11 #205318 by Creative25
Replied by Creative25 on topic LinuxCNC + Orange Pi
Hi I installed linuxcnc on orange pi pc.
According the quick start guide.
Linux Cnc installed without error.
I can find linuxcnc in the Menu.

But unfortunately no shortcuts to test configurations!

I can find the test ini and hal files in the Install folder.
What do I need to do to get those shortcuts?
Last edit: 08 Apr 2021 15:11 by Creative25.

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09 Apr 2021 06:42 #205395 by MX_Master
Replied by MX_Master on topic LinuxCNC + Orange Pi
Good news here :)

I need this project for my main CNC router. So I decided to make full project upgrade. At the moment the sources are hidden. New rt kernel and linuxcnc debs are done. New ARISC firmware and new all-in-one driver are done too. New installer - in the process. Need some time to test the results with logic analyzer, steps counter and a real machine.
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09 Apr 2021 21:20 #205477 by Bari
Replied by Bari on topic LinuxCNC + Orange Pi
@MX_Master I noticed that you have not chosen a license yet for your source. What are your intentions for this? gitlab.com/orangecnc

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10 Apr 2021 04:30 #205496 by MX_Master
Replied by MX_Master on topic LinuxCNC + Orange Pi

Bari wrote: @MX_Master I noticed that you have not chosen a license yet for your source. What are your intentions for this? gitlab.com/orangecnc

There is no license. Anyone can copy this project and add any own license. And then he can sue me for the unlicensed use of his (my) code :)

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10 Apr 2021 04:42 - 10 Apr 2021 05:43 #205500 by tjtr33
Replied by tjtr33 on topic LinuxCNC + Orange Pi
MX_Master, thanks for still working on this. I have been working on a new arisc stepgen and aric gpio. Is there anything I can help with? I have Opi+2e and Tek scope. I am familiar with the original code (JMK) but very new at your structure of using the ports ( more i/o than on the 40 pin header! nice ).
edit: there were complaints that there were lost steps. When i examined the code I did not see use of dirsetup or dirchange. So I went back to JMK's original parport stepgen module. I have not compiled it for aris yet. Do you have direction for how to build new arsic modules?
Thanks
TomP tjtr33
Last edit: 10 Apr 2021 05:43 by tjtr33. Reason: unsaid reasons

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