developing drivers for custom boards

After a wonderful conversation with Peter at MESA, I have ordered a 5i25 to solve my needs. I may move away from the EPP altogether as he has pointed out some better options based on the 5i25.

YEA Thanks Peter!!!

As a followup in case anybody comes across this, my NetMos 9815 based PCI parallel port card fails as predicted when attempting to use it in EPP mode. there seems to be 2 issues -

First it needs a delay or something between consecutive writes, when I added a dummy read between writes, that part seems to work fine.

Second - and more fatal - it does not seem to read the data port pins. so any read just returns the value last sent from a write. Now it seems to me there must be a way around this, but I am content to give up on it. WAY TOO many before me have also condemed this chip, so it is still the same in 2013.

btvpimill wrote:

As a followup in case anybody comes across this, my NetMos 9815 based PCI parallel port card fails as predicted when attempting to use it in EPP mode. there seems to be 2 issues -

First it needs a delay or something between consecutive writes, when I added a dummy read between writes, that part seems to work fine.

Second - and more fatal - it does not seem to read the data port pins. so any read just returns the value last sent from a write. Now it seems to me there must be a way around this, but I am content to give up on it. WAY TOO many before me have also condemed this chip, so it is still the same in 2013.

You need to disable the write drivers on all EPP ports to be able to read from the port.
Just commanding a read of the data port does NOT automatically do this! So, you
have to set/clear bits in the control register to switch between write and read.
These are the same bits used to switch a bidirectional parallel port from read
to write. This applies to all EPP ports, not just the Netmos.

Jon

So this is something BIOS does for us on a built in port? I can do that, but it seems a bit cumbersome. And now I am just whining, seems like that should be built in the same as hand shaking is.

But THANK You Jon, this will bet tested today.

Thats not how EPP hardware works in my experience, read/write is automatically
handled by the EPP state machine. A data write from the host will assert NWrite and
enable the output data buffers, and then assert data strobe, and then wait for nWait to
be de-asserted. A data read will first disable the data buffers, and then assert the data strobe
waiting for de-assertion of nWait (and putting the processor in a wait state until complete)

You _can_ override the EPP directions via the control register but normally the control register
need not be touched for EPP data read, EPP data write, EPP address read, and EPP address write.

Thanks Jon and PCW, I am going away from EPP altogether in favor of MESA 5125.

btvpimill wrote:

So this is something BIOS does for us on a built in port? I can do that, but it seems a bit cumbersome. And now I am just whining, seems like that should be built in the same as hand shaking is.

No, the BIOS only does initial setup before OS startup. Part of the EPP spec
says that the driver needs to flip the port from input to output by setting
the bit in the control register that controls the output drivers on the
data port. It has nothing to do with the built in vs. plug-in card. Maybe if
there is a BIOS routine that does EPP-mode transfers, you could call
it, but it sounds VERY dangerous to call BIOS routines from real-time
code. (I also doubt the BIOS has callable routines for EPP transfers.)

Jon

So before I start reading after I have written, I need to flip the direction in the DCR.
AND
before I start writing after I have written I need to flip it again.

Or better put, my read routines should start by setting the direction to input and my write routines should start by setting direction to output?

And no, I won't be trying to call ANY bios routines - ever!

PCW wrote:

Thats not how EPP hardware works in my experience, read/write is automatically
handled by the EPP state machine. A data write from the host will assert NWrite and
enable the output data buffers, and then assert data strobe, and then wait for nWait to
be de-asserted. A data read will first disable the data buffers, and then assert the data strobe
waiting for de-assertion of nWait (and putting the processor in a wait state until complete)

You _can_ override the EPP directions via the control register but normally the control register
need not be touched for EPP data read, EPP data write, EPP address read, and EPP address write.

Wow! This is VERY interesting! I can report that on SOME chip implementations
of the IEEE-1284 spec, this does NOT work right. My drivers always set the control
register bit for bidirectional read/write before initiating the EPP operation.

I will have to experiment and see which chips do and don't handle this
automatically. (Hmm, there may also be a setup time issue with this,
such that the WRITE/ line changes state AFTER the strobe is issued
if you let it do it automatically, but if you do it through the control register
first, then WRITE/ has at least a few hundred ns of setup time.)

Jon

btvpimill wrote:

So before I start reading after I have written, I need to flip the direction in the DCR.
AND
before I start writing after I have written I need to flip it again.

Or better put, my read routines should start by setting the direction to input and my write routines should start by setting direction to output?

And no, I won't be trying to call ANY bios routines - ever!

That's how I do it in my drivers.

Jon