ColorCNC Colorlight 5A-75E/5A-75B as FPGA controller board

I am interested. I saw in th downloads that the PDF with the schematics something went wrong with the export. Each page is shifted a little bit downwards in the margins, so the last pages are mostly blank.

Would be wonderful to have a sort of HAT for the 5A-75E with for example:
- 6 stepgens (with DIR, STEP, ENA and ALARM (input)) = >24 pins
- 6 PWM with 0 - 10 Volt ouput
- some GPIO - in (for limit switches, button encoders, etc). How many?
- some GPIO - out - how many do we need?
- 1 or two expansion slots for future developments (like MPG, LCD or sensors?

I finished the split between stepgen and pos2vel-converter. I will push that tonight, as I need to add the example how to connect is in the HAL. Runs smoother then ever before.

I pushed the separated stepgen and converter to my GitHub in the branch stepgen_improvement. To use this version, one must modify their HAL-file, below is an example for a single axis.
Edit:
I removed the known issues, as they are now solved in the driver. Also updated the example with the revised pins.

To create an I/O hat for the 5A-75E, I'm wondering whether somebody has:

• A CAD or GERBER-file with the precise locations of the headers of the FPGA controller board
• Some detailed pictures (or just IC numbers) of a MESA card. I'm really wondering how they buffer / isolate their in- and outputs.

 /

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---

/

 Yosys 0.8 (git sha1 5706e90)


-- Executing script file `colorlight_5a_75e.ys' --

1. Executing Verilog-2005 frontend.
Parsing Verilog input from `/home/wuya/LiteX-CNC/5a-75e/gateware/colorlight_5a_75e.v' to AST representation.
Storing AST representation for module `$abstract\colorlight_5a_75e'.
Successfully finished Verilog frontend.

2. Executing ATTRMAP pass (move or copy attributes).

3. Executing SYNTH_ECP5 pass.

3.1. Executing Verilog-2005 frontend.
Parsing Verilog input from `/usr/bin/../share/yosys/ecp5/cells_sim.v' to AST representation.
Lexer warning: The SystemVerilog keyword `assert' (at /usr/bin/../share/yosys/ecp5/cells_sim.v:409) is not recognized unless read_verilog is called with -sv!
Lexer warning: The SystemVerilog keyword `assert' (at /usr/bin/../share/yosys/ecp5/cells_sim.v:410) is not recognized unless read_verilog is called with -sv!
Lexer warning: The SystemVerilog keyword `assert' (at /usr/bin/../share/yosys/ecp5/cells_sim.v:411) is not recognized unless read_verilog is called with -sv!
Lexer warning: The SystemVerilog keyword `assert' (at /usr/bin/../share/yosys/ecp5/cells_sim.v:412) is not recognized unless read_verilog is called with -sv!
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_SLICE'.
Successfully finished Verilog frontend.

3.2. Executing HIERARCHY pass (managing design hierarchy).

3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\colorlight_5a_75e'.
Generating RTLIL representation for module `\colorlight_5a_75e'.

3.3.1. Analyzing design hierarchy..
Top module:  \colorlight_5a_75e
ERROR: Module `\IDDRX1F' referenced in module `\colorlight_5a_75e' in cell `\IDDRX1F_4' is not part of the design.
I got an error compiling the firmware, I don't know why
 

Please share:
- the version of Litex.
- the branch of Litex-CNC you have used. The current branch with the latest updates is 'stepgen_improvement'.
- your configuration file used to create the bit-file.
- the type and make of your Led card, maybe it is the wrong type or you've found an incompatible version. The tool Yosys is only for Lattice ECP FPGA's and not for the RV901 which has a Spartan chipset.

For readability of the forum, please use the code tags to include the log on the forum.

mkdir LiteX
cd LiteX
wget raw.githubusercontent.com/enjoy-digital/...aster/litex_setup.py
python3 litex_setup.py --init --install --config=standard --gcc=riscv
git clone github.com/Peter-van-Tol/LiteX-CNC.git
install yosys
wget github.com/YosysHQ/oss-cad-suite-build/r...nux-x64-20220227.tgz && \
tar -xvf oss-cad-suite-linux-x64-20220227.tgz -C /opt/ && \
rm oss-cad-suite-linux-x64-20220227.tgz && \
echo '# set PATH so it includes oss-cad-suite' >> /etc/profile && \
echo 'if [ -d "/opt/oss-cad-suite/bin" ] ; then' >> /etc/profile && \
echo 'PATH="/opt/oss-cad-suite/bin:$PATH"' >> /etc/profile && \
echo 'fi' >> /etc/profile
5A-75E colorlight used,Command python3 -m firmware examples/5a-75e.json