ColorCNC Colorlight 5A-75E/5A-75B as FPGA controller board

I also think the names of the pins can be useful. My proposal for self-identification was to make the (possibly compressed) json file accesible to the host by some means, either by memory mapping it or by storing it in the flash and let the host read it from there. So only the IP address remains to be configured.

Not sure if the capability to reduce the clock via json is a useful feature. Either a high clock is not necessary, then we can always go with a low clock, or a minimum frequency is needed, in that case it should be allowed to go below that. Why not just pick a low value that's easy to implement for all?

I already went through the config change yesterday, my day ended with a ping reply from my rv901t As you already hinted at I had to change the constraint file manually. I filed an issue for that, github.com/enjoy-digital/litex/issues/1502

About the clock frequency: it is still the 125 MHz clock which is the limiting factor (error in timing). Whether it is useful to have a user configurable clock frequency: I think so. There will be always users wanting to tweak it; for the normal users they can just let it be the default setting. A sensible value for that we have of course to determine.

At this moment I shift focus to create some HUB75 breakout boards for the different functions. All boards have standard dimension of 85 x 56 mm (equal to a Raspberry Pi, although mounting holes are not aligned). At this moment I have designed:

• HUB-75 -> Stepgen differential
  Breakout board which converts 2HUB-75 connectors to 3 stepgen outputs using differential pairs (5V) for high speed operation up to 400 kHz. The enable signal for the stepper drivers is shared. Per channel the ENA can be selected as either active HIGH or active LOW using a DIP-switch. On the board is also a HUB-75 connector for ALARM input, which can also be selected as active HIGH or active LOW with a DIP-switch. Two boards can share 1 HUB-75 input connector (total 6 inputs, for each ALARM one).
• GPIO -> HUB-75 (sinking input)
  Break-out board which supplies 12 sinking inputs, requires 2 HUB-75 input connectors. The inputs are 5-24 Volt tolerant and are isolated from the FPGA using opto-couplers (LTV827). All inputs have indicator LED's to show which input is active. Designed for PNP limit switches and buttons which switch to VField. Each input is a JST connector with three pins, supplying VField, GND and Signal, so limit switches can be easily connected. Can also be used for encoders, but is limited to approximately 1~10 kHz; for faster encoders a different breakout board will be developed.
• HUB-75 -> GPIO (sourcing output)
  Break-out board which supplies 12 sourcing outputs, requires 2 HUB-75 output connectors. Field power can be in the range of 5-24 Volts. Isolated from the FPGA with opto-couplers (LTV827). High side switching using P-channel MOSFETs, which can deliver up to 300 mA per channel.  All outputs have indicator LED's to show which output is active. Each output is a 2-pin JST connector positive and negative (GND) terminal. Designed for a frequency of 1 kHz, but will most-likely support a higher frequency.

My TODO-list:

• Add reverse polarity protection on field power and maybe also a power-indicator;
• Create a board for fast encoders using a RSS-422 chipset for accepting differential input;
• Put the boards on GITHub with a nice description

I try to finish these boards this week so I can order prototypes

The board has some unused space in flash memory and it's available through etherbone access or at compile time by modification of building script.

The answer is that mesa boards use self-designed CPU that is programmed in assembler and its own toolchain to write such a programs. Also mesa boards integrate a hardware ethernet MAC. In contrary to mesa, litex implements UDP/IP stack right in the FPGA. Such a concept is dictated by schematics of existing colorlight boards that connect ethernet physics directly to FPGA chip. Therefore, we __have__ to have a MAC and UDP/IP level in FPGA design. Making litexcnc project compatible with mesa protocol is possible, because out-of-the-box litex offers several risc-v based cpus with some examples. That lowers entry threshold in world of system-on-chips. But except of implementation of flexible computer-independent safety featurs I don't see any reason to go in this direction

I see the logical continuation is to create own FPGA board and use ethercat protocol instead of udp/ip

Some previews of a break-out board for HUB-75.

FRONT:

BACK

I would love to put the LinuxCNC logo on it, but I'm wondering whether that would be allowed...