Here was the slide for The Jetson module itself:
Someone took a picture of the DevKit carrier board without the module installed:
You can see the RPi-like header on the left - a UART in the lower right corner, a MIPI camera connector, M.2 e-Key connector (where you'd put WiFi). This shouldn't be a bit issue - there looks to be about 20 or so GPIO pins available on the header (some are claimed by SPI or I2C busses, of which there are multiples). Using very simple low-level logic, you can expand out to many more IO. As an example, you can use a
3-to-8 address decoder
to multiplex 16 pins to 8x 16-bit registers. With
8-bit D-type latches
, you can do both level-shifting and handle the storage(outputs)+blocking(inputs) of the expanded bits.
With a low level C-driver that has direct access to the memory registers for GPIO (GPIO DMA), you can update all IO bits at once, 16-bits at a time - should be able to hit megahertz speeds for 128-bits at the "bus" - way beyond what LinuxCNC would need. With careful design you can make all of the Outputs update at one time, and simultaneously latch in the Inputs, at roughly 1/16th the Nano's GPIO pin update rate. Using an external clock that runs a counter, you can throw an interrupt to run the low-level parallel bus data driver rather than non-deterministic timing inside the ARM.
You'd still have I2C, SPI, USB, PCIe, and network interfaces available for other uses using this method too. Point is, there's probably a way to get there as long as we can get the core functionality working - the real-time kernel patch, the Nvidia driver playing nice with it, and checking that the system jitter is in spec.
Mine shipped from Sparkfun last week and should be here tomorrow. I'm thinking of going the above route if I can get LinuxCNC to play nice with the Jetson Nano - except I'll probably use a pair of
TI DS92LV18 Ser/Des
and some standard SFP 1GBe transceiver modules to optically isolate the controller from the power switching drivers. Running the ser/des isolator at 50MHz and clocking in the data from the Nano at 6.25MHz - that gives about a 160nS GPIO refresh rate. Again, assuming it all works
