newbie failed to compile Bitfile

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14 Feb 2019 23:48 - 15 Feb 2019 00:11 #126505 by dremeier
Hello Guys,

I received my Mesa-Set:
-7I44 Eight Channel RS-422/485 interface/ RJ45 Breakout
-7I87 Remote isolated Analog input card
-7I47S 8/12 Channel motion oriented RS-422 interface with analog out
-7I90HD Parallel/SPI Anything I/O card
-6I24-25 FPGA based PCI Anything I/O card

I installed ISE Design Suit 14.7 on Debian.
Loaded the sources "fivei24"
Edit the FPGA to xc6slx25-2ftg256
copy a suitable Pin-file, renamed it and edit as follow:
library IEEE;
use IEEE.std_logic_1164.all;  -- defines std_logic types
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- edit by Andre Meier
--  

use work.IDROMConst.all;

package PIN_2x7i74s_1x7i44_72_andre is
	constant ModuleID : ModuleIDType :=( 
		(WatchDogTag,	x"00",	ClockLowTag,	x"01",	WatchDogTimeAddr&PadT,		WatchDogNumRegs,		x"00",	WatchDogMPBitMask),
		(IOPortTag,		x"00",	ClockLowTag,	x"03",	PortAddr&PadT,					IOPortNumRegs,			x"00",	IOPortMPBitMask),
		(QcountTag,		x"02",	ClockLowTag,	x"08",	QcounterAddr&PadT,			QCounterNumRegs,		x"00",	QCounterMPBitMask),
		(PWMTag,			x"00",	ClockHighTag,	x"02",	PWMValAddr&PadT,				PWMNumRegs,				x"00",	PWMMPBitMask),
		(StepGenTag,	x"02",	ClockLowTag,	x"08",	StepGenRateAddr&PadT,		StepGenNumRegs,		x"00",	StepGenMPBitMask),
		(SSerialTag,	x"00",	ClockLowTag,	x"01",	SSerialCommandAddr&PadT,	SSerialNumRegs,		x"10",	SSerialMPBitMask),
		(LEDTag,			x"00",	ClockLowTag,	x"01",	LEDAddr&PadT,					LEDNumRegs,				x"00",	LEDMPBitMask),
		(NullTag,		x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,		x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,		x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,		x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,		x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,		x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,		x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,		x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,		x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,		x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,		x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,		x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,		x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,		x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,		x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,		x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,		x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,		x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,		x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,		x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,		x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,		x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,		x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,		x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(NullTag,		x"00",	NullTag,			x"00",	NullAddr&PadT,					x"00",					x"00",	x"00000000")
		);
		
	
	constant PinDesc : PinDescType :=(
-- 	Base func  sec unit sec func 	 sec pin					P1 7i47s
		IOPortTag & x"00" & StepGenTag & StepGenStepPin,	-- I/O 00  TX4
		IOPortTag & x"00" & StepGenTag & StepGenDirPin,		-- I/O 01  TX5	
		IOPortTag & x"01" & StepGenTag & StepGenStepPin,	-- I/O 02  TX6		
		IOPortTag & x"01" & StepGenTag & StepGenDirPin,		-- I/O 03  TX7		
		IOPortTag & x"00" & QCountTag & QCountQAPin,			-- I/O 04  RX0		
		IOPortTag & x"02" & QCountTag & QCountQAPin,			-- I/O 05		
		IOPortTag & x"00" & QCountTag & QCountQBPin,			-- I/O 06  RX1			
		IOPortTag & x"02" & QCountTag & QCountQBPin,			-- I/O 07		
		IOPortTag & x"00" & QCountTag & QCountIDXPin,		-- I/O 08  RX2		
		IOPortTag & x"02" & QCountTag & QCountIDXPin,		-- I/O 09
		IOPortTag & x"01" & QCountTag & QCountQAPin,			-- I/O 10
		IOPortTag & x"03" & QCountTag & QCountQAPin,			-- I/O 11
		IOPortTag & x"01" & QCountTag & QCountQBPin,			-- I/O 12		
		IOPortTag & x"03" & QCountTag & QCountQBPin,			-- I/O 13	
		IOPortTag & x"01" & QCountTag & QCountIDXPin,		-- I/O 14	
		IOPortTag & x"03" & QCountTag & QCountIDXPin,		-- I/O 15
		IOPortTag & x"00" & NullTag & x"00",					-- I/O 16 7I47S SPARE ISOLATED OUT
		IOPortTag & x"00" & PWMTag  & PWMBDirPin,				-- I/O 17 7I47S DIRECTION	
		IOPortTag & x"00" & PWMTag  & PWMCEnaPin,				-- I/O 18 7I47S PWMENABLE			
		IOPortTag & x"00" & PWMTag  & PWMAOutPin,				-- I/O 19 7I47S PWMOUT	
		IOPortTag & x"02" & StepGenTag & StepGenStepPin,	-- I/O 20  TX0		
		IOPortTag & x"02" & StepGenTag & StepGenDirPin,		-- I/O 21  TX1
		IOPortTag & x"03" & StepGenTag & StepGenStepPin,	-- I/O 22  TX2			
		IOPortTag & x"03" & StepGenTag & StepGenDirPin,		-- I/O 23  TX3

--																			P2 7i47s
		IOPortTag & x"04" & StepGenTag & StepGenStepPin,	-- I/O 00  TX4
		IOPortTag & x"04" & StepGenTag & StepGenDirPin,		-- I/O 01  TX5	
		IOPortTag & x"05" & StepGenTag & StepGenStepPin,	-- I/O 02  TX6		
		IOPortTag & x"05" & StepGenTag & StepGenDirPin,		-- I/O 03  TX7		
		IOPortTag & x"04" & QCountTag & QCountQAPin,			-- I/O 04  RX0		
		IOPortTag & x"06" & QCountTag & QCountQAPin,			-- I/O 05		
		IOPortTag & x"04" & QCountTag & QCountQBPin,			-- I/O 06  RX1			
		IOPortTag & x"06" & QCountTag & QCountQBPin,			-- I/O 07		
		IOPortTag & x"04" & QCountTag & QCountIDXPin,		-- I/O 08  RX2		
		IOPortTag & x"04" & QCountTag & QCountIDXPin,		-- I/O 09
		IOPortTag & x"05" & QCountTag & QCountQAPin,			-- I/O 10
		IOPortTag & x"07" & QCountTag & QCountQAPin,			-- I/O 11
		IOPortTag & x"05" & QCountTag & QCountQBPin,			-- I/O 12		
		IOPortTag & x"07" & QCountTag & QCountQBPin,			-- I/O 13	
		IOPortTag & x"05" & QCountTag & QCountIDXPin,		-- I/O 14	
		IOPortTag & x"07" & QCountTag & QCountIDXPin,		-- I/O 15
		IOPortTag & x"00" & NullTag & x"00",					-- I/O 16 7I47S SPARE ISOLATED OUT
		IOPortTag & x"01" & PWMTag  & PWMBDirPin,				-- I/O 17 7I47S DIRECTION	
		IOPortTag & x"01" & PWMTag  & PWMCEnaPin,				-- I/O 18 7I47S PWMENABLE			
		IOPortTag & x"01" & PWMTag  & PWMAOutPin,				-- I/O 19 7I47S PWMOUT	
		IOPortTag & x"06" & StepGenTag & StepGenStepPin,	-- I/O 20  TX0		
		IOPortTag & x"06" & StepGenTag & StepGenDirPin,		-- I/O 21  TX1
		IOPortTag & x"07" & StepGenTag & StepGenStepPin,	-- I/O 22  TX2			
		IOPortTag & x"07" & StepGenTag & StepGenDirPin,		-- I/O 23  TX3

--																			P3 7i44 8x sserial																	
		IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, 	-- I/O 48
		IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, 	-- I/O 49
		IOPortTag & x"00" & SSerialTag & SSerialRX2Pin, 	-- I/O 50
		IOPortTag & x"00" & SSerialTag & SSerialRX3Pin, 	-- I/O 51
		IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, 	-- I/O 52
		IOPortTag & x"00" & SSerialTag & SSerialTXEn0Pin,	-- I/O 53
		IOPortTag & x"00" & SSerialTag & SSerialTX1Pin,		-- I/O 54
		IOPortTag & x"00" & SSerialTag & SSerialTXEn1Pin,	-- I/O 55
		IOPortTag & x"00" & SSerialTag & SSerialTX2Pin, 	-- I/O 56
		IOPortTag & x"00" & SSerialTag & SSerialTXEn2Pin,	-- I/O 57
		IOPortTag & x"00" & SSerialTag & SSerialTX3Pin, 	-- I/O 58
		IOPortTag & x"00" & SSerialTag & SSerialTXEn3Pin,	-- I/O 59
		IOPortTag & x"00" & SSerialTag & SSerialRX4Pin, 	-- I/O 60
		IOPortTag & x"00" & SSerialTag & SSerialRX5Pin,   	-- I/O 61
		IOPortTag & x"00" & SSerialTag & SSerialRX6Pin,   	-- I/O 62
		IOPortTag & x"00" & SSerialTag & SSerialRX7Pin, 	-- I/O 63
		IOPortTag & x"00" & SSerialTag & SSerialTX4Pin,   	-- I/O 64
		IOPortTag & x"00" & SSerialTag & SSerialTXEn4Pin,  -- I/O 65
		IOPortTag & x"00" & SSerialTag & SSerialTX5Pin,		-- I/O 66
		IOPortTag & x"00" & SSerialTag & SSerialTXEn5Pin,	-- I/O 67
		IOPortTag & x"00" & SSerialTag & SSerialTX6Pin, 	-- I/O 68
		IOPortTag & x"00" & SSerialTag & SSerialTXEn6Pin,  -- I/O 69
		IOPortTag & x"00" & SSerialTag & SSerialTX7Pin,   	-- I/O 70
		IOPortTag & x"00" & SSerialTag & SSerialTXEn7Pin,  -- I/O 71
                                                   
		emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
		emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
					
		emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
		emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
		emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
		emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
		emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
		emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
		emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);

end package PIN_2x7i74s_1x7i44_72_andre;

also edit the TopPCIHostMot2.vhd (full as attached)

Attachment not found

:
--use work.@Card@.all;

--use work.i25_x9card.all; 		-- needs 5i25.ucf and SP6 x9 144 pin

--use work.i74_x9card.all;   	-- needs 4I74.ucf and SP6 x9 144 pin

--use work.Sixi25_x9card.all;	-- needs 5i25.ucf and SP6 x9 144 pin

--use work.i24_x16card.all; 	-- needs 5I24.ucf and SP6 x16 256 pin

use work.i24_x25card.all;   -- needs 5I24.ucf and SP6 x25 256 pin



-----------------------------------------------------------------------





-------------------- select (or add) one pinout -----------------------

--use work.@Pin@.all;

use work.PIN_2x7i74s_1x7i44_72_andre.all;

-- 34 I/O pinouts for 5I25, 5I26 and 6I25:


If I run "Generate Programming File" I got "Process "Generate Programming File" completed successfully" but I´ve a lot of Warnings, I don´t want to ignore. The Warnings also attached.

Attachment not found

Does someone has a suggestion how to correct this?

I also don´t understand how to count the Tags I want, StepGens are clear, but for example the sserial states just 01 "(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommand...." but I´ve 8. (I copied from other files with 8 sserial). Maybe somone can explain the lines in the PIN_files.vdh ?

Thanks
Andre

File Attachment:

File Name: TopPCIHost...2-14.txt
File Size:34 KB

File Attachment:

File Name: Warnings_2...2-14.txt
File Size:53 KB
Attachments:
Last edit: 15 Feb 2019 00:11 by dremeier.

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15 Feb 2019 00:23 - 15 Feb 2019 00:54 #126508 by PCW
1. Its not possible to get rid of all warnings (you can do a lot of work and _change_ the warnings somewhat if you like)
2. Sserial modules have 1 to 8 channels each (there can be a maximum of 4 sserial modules in a configuration)
3. The module ID fields are as follows:

type ModuleRecord is -- probably need an alternate way for smart modules
record
GTag : std_logic_vector(7 downto 0);
Version : std_logic_vector(7 downto 0);
Clock : std_logic_vector(7 downto 0);
NumInstances : std_logic_vector(7 downto 0);
BaseAddr : std_logic_vector(15 downto 0);
NumRegisters : std_logic_vector(7 downto 0);
Strides : std_logic_vector(7 downto 0);
MultRegs : std_logic_vector(31 downto 0);
end record;
Last edit: 15 Feb 2019 00:54 by PCW.
The following user(s) said Thank You: dremeier

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15 Feb 2019 00:41 #126512 by dremeier
Thanks PCW,

So I can give the bitfile a try.
nevertheless, are you performing a bitfile for me? I wrote you a email(order nr. 5142)
I don´t trust my file. :-)

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15 Feb 2019 11:06 #126532 by dremeier

1. Its not possible to get rid of all warnings (you can do a lot of work and _change_ the warnings somewhat if you like)
2. Sserial modules have 1 to 8 channels each (there can be a maximum of 4 sserial modules in a configuration)
3. The module ID fields are as follows:

type ModuleRecord is -- probably need an alternate way for smart modules
record
GTag : std_logic_vector(7 downto 0);
Version : std_logic_vector(7 downto 0);
Clock : std_logic_vector(7 downto 0);
NumInstances : std_logic_vector(7 downto 0);
BaseAddr : std_logic_vector(15 downto 0);
NumRegisters : std_logic_vector(7 downto 0);
Strides : std_logic_vector(7 downto 0);
MultRegs : std_logic_vector(31 downto 0);
end record;


In wich file I have to put this ^^ in?

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15 Feb 2019 15:28 #126556 by PCW
That is already part of the source

(in IDROMConsts.vhd)

I can build that bitfile if you like, it woudl save some time if you sent me the PIN_XXX file

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15 Feb 2019 16:26 #126567 by dremeier
Here the Pin File:

File Attachment:

File Name: PIN_2x7i74....vhd.txt
File Size:9 KB


I´will have a look an your sources to figure out my mistakes. :-)

Thanks a lot
Attachments:

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20 Feb 2019 07:50 #126807 by dremeier
please, can I remind you to build an bitfile for me?
Thanks in advanced

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20 Feb 2019 16:12 #126823 by PCW
Your pin file looked ok to me (except the name)

freeby.mesanet.com/5i24_25_2x7i47s_7i44.bit

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21 Feb 2019 10:31 #126855 by dremeier
Ok, thank you

did you changes in the IDROMConsts.vhd or anywhere else?
What is wrong withe the name?

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21 Feb 2019 12:56 #126856 by PCW
No, no changes anywhere but the PIN_XXX file and the top level file to add the pin file

(just changed the file/package name from 2X7I74S_7I44 to 2X7I47S_7I44 which doesn't affect the bitfile)

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